公开(公告)号：US11693667B2

公开(公告)日：2023-07-04

申请号：US17692571

申请日：2022-03-11

Applicant: NVIDIA Corporation

Inventor： Joshua Patterson ,  Leeann Chau Tuyet Dang ,  Keith Jason Kraus ,  Allan Rabbitt Enemark ,  Frank Joseph Eaton ,  Bradley Stuart Rees ,  Michael Evan Wendt ,  Mark Jason Harris

IPC: G06F13/16 ,  G06N20/00 ,  G06N3/02 ,  G06F9/38 ,  G06N3/08 ,  G06F9/30 ,  G06T1/20

CPC classification number: G06F9/3881 ,  G06F9/30043 ,  G06F9/3822 ,  G06F13/1663 ,  G06N3/02 ,  G06N3/08 ,  G06N20/00 ,  G06T1/20 ,  G06F2009/3883

Abstract: Systems and methods are provided for efficiently performing processing intensive operations, such as those involving large volumes of data, that enable accelerated processing time of these operations. In at least one embodiment, a system includes a graphics processor unit (GPU) including a memory and a plurality of cores. The plurality of cores perform a plurality of data analytics operations on a respectively allocated portion of a dataset, each of the plurality of cores using only the memory to store data input for each of the plurality of data analytics operations performed by the plurality of cores. The data storage for the plurality of data analytics operations performed by the plurality of cores is also provided solely by the memory.

公开(公告)号：US12141582B2

公开(公告)日：2024-11-12

申请号：US17936172

申请日：2022-09-28

Applicant: NVIDIA CORPORATION

Inventor： Maciej Piotr Tyrlik ,  Ajay Sudarshan Tirumala ,  Shirish Gadre ,  Frank Joseph Eaton ,  Daniel Alan Stiffler

IPC: G06F9/30 ,  G06F9/38

Abstract: Various techniques for accelerating dynamic programming algorithms are provided. For example, a fused addition and comparison instruction, a three-operand comparison instruction, and a two-operand comparison instruction are used to accelerate a Needleman-Wunsch algorithm that determines an optimized global alignment of subsequences over two entire sequences. In another example, the fused addition and comparison instruction is used in an innermost loop of a Floyd-Warshall algorithm to reduce the number of instructions required to determine shortest paths between pairs of vertices in a graph. In another example, a two-way single instruction multiple data (SIMD) floating point variant of the three-operand comparison instruction is used to reduce the number of instructions required to determine the median of an array of floating point values.

公开(公告)号：US20230145783A1

公开(公告)日：2023-05-11

申请号：US17521440

申请日：2021-11-08

Applicant: NVIDIA Corporation

Inventor： Mehmet Akif Çördük ,  Frank Joseph Eaton ,  Alexandre Jacques Antoine Fender ,  Hugo Linsenmaier ,  Shankara Rao Thejaswi Nanditale

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/455 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/3877 ,  G06F9/5072 ,  G06F9/45558 ,  G06F2009/4557

Abstract: In various examples, solutions to combinatorial optimization problems are determined using a plurality of solvers executing in parallel. In an embodiment, the plurality of solvers executed in parallel perform one or more search algorithms. Furthermore, in such embodiments, the operations of the one or more search algorithms are also executed in parallel.

公开(公告)号：US20220197664A1

公开(公告)日：2022-06-23

申请号：US17692571

申请日：2022-03-11

Applicant: NVIDIA Corporation

Inventor： Joshua Patterson ,  Leeann Chau Tuyet Dang ,  Keith Jason Kraus ,  Allan Rabbitt Enemark ,  Frank Joseph Eaton ,  Bradley Stuart Rees ,  Michael Evan Wendt ,  Mark Jason Harris

IPC: G06F9/38 ,  G06N3/02 ,  G06N20/00 ,  G06N3/08 ,  G06T1/20 ,  G06F9/30

Abstract: Systems and methods are provided for efficiently performing processing intensive operations, such as those involving large volumes of data, that enable accelerated processing time of these operations. In at least one embodiment, a system includes a graphics processor unit (GPU) including a memory and a plurality of cores. The plurality of cores perform a plurality of data analytics operations on a respectively allocated portion of a dataset, each of the plurality of cores using only the memory to store data input for each of the plurality of data analytics operations performed by the plurality of cores. The data storage for the plurality of data analytics operations performed by the plurality of cores is also provided solely by the memory.

公开(公告)号：US11307863B1

公开(公告)日：2022-04-19

申请号：US16596755

申请日：2019-10-08

Applicant: NVIDIA Corporation

Inventor： Joshua Patterson ,  Leeann Chau Tuyet Dang ,  Keith Jason Kraus ,  Allan Rabbitt Enemark ,  Frank Joseph Eaton ,  Bradley Stuart Rees ,  Michael Evan Wendt ,  Mark Jason Harris

IPC: G06N3/08 ,  G06N3/02 ,  G06N20/00 ,  G06T1/20 ,  G06F9/38 ,  G06F9/30

Abstract: Systems and methods are provided for efficiently performing processing intensive operations, such as those involving large volumes of data, that enable accelerated processing time of these operations. In at least one embodiment, a system includes a graphics processor unit (GPU) including a memory and a plurality of cores. The plurality of cores perform a plurality of data analytics operations on a respectively allocated portion of a dataset, each of the plurality of cores using only the memory to store data input for each of the plurality of data analytics operations performed by the plurality of cores. The data storage for the plurality of data analytics operations performed by the plurality of cores is also provided solely by the memory.