公开(公告)号：US09817670B2

公开(公告)日：2017-11-14

申请号：US14105349

申请日：2013-12-13

申请人： International Business Machines Corporation

发明人： Nitin Gupta ,  Mehulkumar J. Patel ,  Deepak C. Shetty

IPC分类号： G06F15/76 ,  G06F9/46 ,  G06F9/38 ,  G06F9/54 ,  G06F9/48

CPC分类号： G06F9/3877 ,  G06F9/3879 ,  G06F9/4881 ,  G06F9/547 ,  G06F15/7889 ,  G06F2009/3883 ,  G06F2209/543

摘要： When a main processor issues a command to co-processor, a timeout value is included in the command. As the co-processor attempts to execute the command, it is determined whether the attempt is taking time beyond what is permitted by the timeout value. If the timeout is exceeded then responsive action is taken, such as the generation of a command timeout type failure message. The receipt of the command with the timeout value, and the consequent determination of a timeout condition for the command, may be determined by: the co-processor that receives the command, or a watchdog timer that is separate from the co-processor. Also, detection of co-processor hang and/or hung co-processor conditions during the time that a co-processor is executing a command for the main processor.

公开(公告)号：US20150074374A1

公开(公告)日：2015-03-12

申请号：US14480573

申请日：2014-09-08

申请人： Futurewei Technologies Inc.

发明人： Qifan Zhang ,  Wuxian Shi ,  Yiqun Ge ,  Tao Huang ,  Wen Tong

IPC分类号： G06F9/30 ,  G06F15/78

CPC分类号： G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

摘要： An asynchronous processing system comprising an asynchronous scalar processor and an asynchronous vector processor coupled to the scalar processor. The asynchronous scalar processor is configured to perform processing functions on input data and to output instructions. The asynchronous vector processor is configured to perform processing functions in response to a very long instruction word (VLIW) received from the scalar processor. The VLIW comprises a first portion and a second portion, at least the first portion comprising a vector instruction.

摘要翻译： 包括异步标量处理器和耦合到标量处理器的异步向量处理器的异步处理系统。 异步标量处理器被配置为对输入数据执行处理功能并输出指令。 异步向量处理器被配置为响应于从标量处理器接收的非常长的指令字（VLIW）执行处理功能。 VLIW包括第一部分和第二部分，至少第一部分包括矢量指令。

公开(公告)号：US20130159664A1

公开(公告)日：2013-06-20

申请号：US13325282

申请日：2011-12-14

申请人： Paul BLINZER ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

发明人： Paul BLINZER ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F9/3004 ,  G06F9/3881 ,  G06F12/1081 ,  G06F2009/3883 ,  G06F2212/683

摘要： In a CPU of the combined CPU/APD architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to an APD, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.

摘要翻译： 在组合的CPU / APD架构系统的CPU中，CPU具有多个CPU内核，每个核具有用于接收物理页表/页目录基地址的第一机器特定寄存器，用于接收物理地址指向 到由通信地耦合到APD的IOMMUv2控制的位置，以及当被执行时导致向包含在第二机器特定寄存器中的物理地址发出写入通知的微代码; 在CPU核心的第一机器特定寄存器中接收物理页表/页目录基地址，在CPU核心的第二机器特定寄存器中接收指向由IOMMUv2控制的位置的物理地址，确定控制 已经更新了CPU核心的寄存器，并且响应于控制寄存器被更新的确定，执行CPU核心中的微代码，使得向第二机器特定寄存器中包含的物理地址发出写入通知，其中， 物理地址能够接收影响IOMMUv2页表无效的写入。

公开(公告)号：US20090273491A1

公开(公告)日：2009-11-05

申请号：US12431828

申请日：2009-04-29

申请人： Hiroaki SAKAGUCHI ,  Hiroshi Yoshikawa

发明人： Hiroaki SAKAGUCHI ,  Hiroshi Yoshikawa

IPC分类号： H03M7/00 ,  H03M7/34

CPC分类号： H03M7/4006 ,  G06F9/30018 ,  G06F2009/3883 ,  H04N19/44 ,  H04N19/91

摘要： Disclosed herein is an arithmetic decoding device including: an arithmetic decoding unit configured to decode coded data resulting from arithmetic coding on a basis of a context variable indicating a probability state and a most probable symbol; a plurality of arithmetic registers configured to supply the context variable to the arithmetic decoding unit and retain a result of operation by the arithmetic decoding unit; and a plurality of save registers configured to save contents retained in the arithmetic registers.

摘要翻译： 本文公开了一种算术解码装置，包括：算术解码单元，被配置为基于指示概率状态的上下文变量和最可能的符号来解码由算术编码产生的编码数据; 多个算术寄存器，被配置为将所述上下文变量提供给所述算术解码单元，并且保留所述算术解码单元的操作结果; 以及多个保存寄存器，被配置为保存保留在算术寄存器中的内容。

公开(公告)号：US09898301B2

公开(公告)日：2018-02-20

申请号：US14310283

申请日：2014-06-20

申请人： International Business Machines Corporation

发明人： Nitin Gupta ,  Mehulkumar J. Patel ,  Deepak C. Shetty

IPC分类号： G06F9/46 ,  G06F15/76 ,  G06F9/38 ,  G06F9/54 ,  G06F9/48 ,  G06F15/78

CPC分类号： G06F9/3877 ,  G06F9/3879 ,  G06F9/4881 ,  G06F9/547 ,  G06F15/7889 ,  G06F2009/3883 ,  G06F2209/543

摘要： When a main processor issues a command to co-processor, a timeout value is included in the command. As the co-processor attempts to execute the command, it is determined whether the attempt is taking time beyond what is permitted by the timeout value. If the timeout is exceeded then responsive action is taken, such as the generation of a command timeout type failure message. The receipt of the command with the timeout value, and the consequent determination of a timeout condition for the command, may be determined by: the co-processor that receives the command, or a watchdog timer that is separate from the co-processor. Also, detection of co-processor hang and/or hung co-processor conditions during the time that a co-processor is executing a command for the main processor.

公开(公告)号：US09740487B2

公开(公告)日：2017-08-22

申请号：US14480522

申请日：2014-09-08

申请人： Huawei Technologies Co., Ltd.

发明人： Tao Huang ,  Qifan Zhang ,  Wuxian Shi ,  Yiqun Ge ,  Wen Tong

IPC分类号： G06F9/30 ,  G06F15/76 ,  G06F1/08 ,  G06F1/10 ,  G06F9/38 ,  G06F9/50

CPC分类号： G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

摘要： A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.

公开(公告)号：US20150074446A1

公开(公告)日：2015-03-12

申请号：US14480531

申请日：2014-09-08

申请人： Futurewei Technologies Inc.

发明人： Wen Tong ,  Yiqun Ge ,  Qifan Zhang ,  Wuxian Shi ,  Huang Tao

IPC分类号： G06F1/08

CPC分类号： G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

摘要： A clock-less asynchronous processing circuit or system utilizes a self-clocked generator to adjust the processing delay (latency) needed/allowed to the processing cycle in the circuit/system. The timing of the self-clocked generator is dynamically adjustable depending on various parameters. These parameters may include processing instruction, opcode information, type of processing to be performed by the circuit/system, or overall desired processing performance. The latency may also be adjusted to change processing performance, including power consumption, speed etc.

摘要翻译： 无时钟异步处理电路或系统利用自定时发生器来调整电路/系统中处理周期所需/允许的处理延迟（等待时间）。 自定时发生器的定时可根据各种参数动态调整。 这些参数可以包括处理指令，操作码信息，由电路/系统执行的处理类型或整体期望的处理性能。 还可以调整延迟以改变处理性能，包括功耗，速度等。

公开(公告)号：US20150074443A1

公开(公告)日：2015-03-12

申请号：US14480491

申请日：2014-09-08

申请人： Futurewei Technologies Inc.

发明人： Tao Huang ,  Qifan Zhang ,  Wuxian Shi ,  Yiqun Ge ,  Wen Tong

IPC分类号： G06F1/08

CPC分类号： G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

摘要： A clock-less asynchronous processing circuit or system is configured to operation in a plurality of modes. In an initialization mode (e.g., reset, initialization, boot up), a self-clocked generator associated with the asynchronous circuit is configured to generate an active complete signal (to latch output processed data) within a first period of time after receiving a trigger signal. In a normal mode, the self-clocked generator is configured to generate the active complete signal within a second period of time after receiving the trigger signal. In one embodiment, during the initialization mode, the asynchronous circuit latches the output slower than when in the normal mode.

摘要翻译： 无时钟异步处理电路或系统被配置为以多种模式操作。 在初始化模式（例如，复位，初始化，启动）中，与异步电路相关联的自定时发生器被配置为在接收到触发之后的第一时间段内产生有效完成信号（锁存输出处理的数据） 信号。 在正常模式下，自定时发生器被配置为在接收到触发信号之后的第二时间段内产生有效完成信号。 在一个实施例中，在初始化模式期间，异步电路比正常模式下的锁存输出慢。

公开(公告)号：US08578129B2

公开(公告)日：2013-11-05

申请号：US13325282

申请日：2011-12-14

申请人： Paul Blinzer ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

发明人： Paul Blinzer ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

IPC分类号： G06F12/00

CPC分类号： G06F12/1009 ,  G06F9/3004 ,  G06F9/3881 ,  G06F12/1081 ,  G06F2009/3883 ,  G06F2212/683

摘要： In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.

摘要翻译： 在CPU中，具有多个CPU核心的CPU，每个核心具有第一机器特定寄存器，第二机器特定寄存器和微代码，当被执行时，将对包含在第二机器特定寄存器中的物理地址发出写入通知; 在CPU核心的第一机器特定寄存器中接收物理页表/页目录基地址，在CPU核心的第二机器特定寄存器中接收指向由IOMMUv2控制的位置的物理地址，确定控制 已经更新了CPU核心的寄存器，并且响应于控制寄存器被更新的确定，执行CPU核心中的微代码，使得向第二机器特定寄存器中包含的物理地址发出写入通知，其中， 物理地址能够接收影响IOMMUv2页表无效的写入。

公开(公告)号：US11693667B2

公开(公告)日：2023-07-04

申请号：US17692571

申请日：2022-03-11

申请人： NVIDIA Corporation

发明人： Joshua Patterson ,  Leeann Chau Tuyet Dang ,  Keith Jason Kraus ,  Allan Rabbitt Enemark ,  Frank Joseph Eaton ,  Bradley Stuart Rees ,  Michael Evan Wendt ,  Mark Jason Harris

IPC分类号： G06F13/16 ,  G06N20/00 ,  G06N3/02 ,  G06F9/38 ,  G06N3/08 ,  G06F9/30 ,  G06T1/20

CPC分类号： G06F9/3881 ,  G06F9/30043 ,  G06F9/3822 ,  G06F13/1663 ,  G06N3/02 ,  G06N3/08 ,  G06N20/00 ,  G06T1/20 ,  G06F2009/3883

摘要： Systems and methods are provided for efficiently performing processing intensive operations, such as those involving large volumes of data, that enable accelerated processing time of these operations. In at least one embodiment, a system includes a graphics processor unit (GPU) including a memory and a plurality of cores. The plurality of cores perform a plurality of data analytics operations on a respectively allocated portion of a dataset, each of the plurality of cores using only the memory to store data input for each of the plurality of data analytics operations performed by the plurality of cores. The data storage for the plurality of data analytics operations performed by the plurality of cores is also provided solely by the memory.