公开(公告)号：US20140129807A1

公开(公告)日：2014-05-08

申请号：US13671485

申请日：2012-11-07

Applicant: NVIDIA CORPORATION

Inventor： David Conrad TANNENBAUM ,  Ming Y. SIU ,  Stuart F. OBERMAN ,  Colin SPRINKLE ,  Srinivasan IYER ,  Ian Chi Yan KWONG

IPC: G06F9/302 ,  G06F9/30

Abstract: A system and method are described for providing hints to a processing unit that subsequent operations are likely. Responsively, the processing unit takes steps to prepare for the likely subsequent operations. Where the hints are more likely than not to be correct, the processing unit operates more efficiently. For example, in an embodiment, the processing unit consumes less power. In another embodiment, subsequent operations are performed more quickly because the processing unit is prepared to efficiently handle the subsequent operations.

Abstract translation: 描述了一种系统和方法，用于向处理单元提供后续操作可能的提示。 响应地，处理单元采取步骤准备可能的后续操作。 在提示更有可能不正确的地方，处理单元更有效地运作。 例如，在一个实施例中，处理单元消耗较少的功率。 在另一个实施例中，由于处理单元被准备好以有效地处理随后的操作，更快地执行后续操作。

公开(公告)号：US20150039662A1

公开(公告)日：2015-02-05

申请号：US13959397

申请日：2013-08-05

Applicant: NVIDIA CORPORATION

Inventor： Srinivasan IYER ,  David Conrad TANNENBAUM ,  Stuart F. OBERMAN ,  Ming (Michael) Y. SIU

IPC: G06F5/01

CPC classification number: G06F5/012 ,  G06F7/483 ,  G06F7/5443

Abstract: A fused floating-point multiply-add element includes a multiplier that generates a product, and a shifter that shifts an addend within a narrow range. Interpreting logic analyzes the magnitude of the addend relative to the product and then causes logic arrays to position the shifted addend within the left, center, or right portions of a composite register depending in the magnitude of the addend relative to the product. The interpreting logic also forces other portions of the composite register to zero. When the addend is zero, the interpreting logic forces all portions of the composite register to zero. Final combining logic then adds the contents of the composite register to the product.

Abstract translation: 融合浮点乘法元素包括产生乘积的乘法器和用于移动窄范围内的加数的移位器。 解释逻辑分析加法相对于产品的大小，然后使逻辑阵列根据相对于产品的加数的大小，将移位的加数定位在复合寄存器的左，中，右部分内。 解释逻辑还强制复合寄存器的其他部分为零。 当加数为零时，解释逻辑强制复合寄存器的所有部分为零。 最终组合逻辑然后将复合寄存器的内容添加到产品中。

公开(公告)号：US20140143564A1

公开(公告)日：2014-05-22

申请号：US13683362

申请日：2012-11-21

Applicant: NVIDIA CORPORATION

Inventor： David Conrad TANNENBAUM ,  Colin SPRINKLE ,  Stuart F. OBERMAN ,  Ming Y. SIU ,  Srinivasan IYER ,  Ian-Chi Yan KWONG

IPC: G06F1/32 ,  G06F7/483

CPC classification number: G06F1/3234 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3287 ,  G06F7/483 ,  G06F7/4876 ,  G06F9/30014 ,  G06F9/30189 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171

Abstract: An approach is provided for enabling power reduction in floating-point operations. In one example, a system receives floating-point numbers of a fused multiply-add instruction. The system determines the fused multiply-add instruction does not require compliance with a standard of precision for floating-point numbers. The system generates gating signals for an integrated circuit that is configured to perform operations of the fused multiply-add instruction. The system then sends the gating signals to the integrated circuit to turn off a plurality of logic gates included in the integrated circuit.

Abstract translation: 提供了一种用于在浮点运算中实现功率降低的方法。 在一个示例中，系统接收融合乘法加法指令的浮点数。 系统确定融合乘法加法指令不需要符合浮点数的精度标准。 该系统为集成电路产生门控信号，该集成电路被配置为执行融合乘法指令的操作。 系统然后将门控信号发送到集成电路以关闭集成电路中包括的多个逻辑门。