TECHNIQUES FOR CONTENT SYNTHESIS USING DENOISING DIFFUSION MODELS

    公开(公告)号:US20230368337A1

    公开(公告)日:2023-11-16

    申请号:US18182271

    申请日:2023-03-10

    CPC classification number: G06T5/002 G06T2207/20081 G06T2207/20084

    Abstract: Techniques are disclosed herein for generating a content item. The techniques include receiving a content item and metadata indicating a level of corruption associated with the content item; and for each iteration included in a plurality of iterations: performing one or more operations to add corruption to a first version of the content item to generate a second version of the content item, and performing one or more operations to reduce corruption in the second version of the content item to generate a third version of the content item, wherein a level of corruption associated with the third version of the content item is less than a level of corruption associated with the first version of the content item.

    TECHNIQUES FOR CONTENT SYNTHESIS USING DENOISING DIFFUSION MODELS

    公开(公告)号:US20230368073A1

    公开(公告)日:2023-11-16

    申请号:US18182283

    申请日:2023-03-10

    CPC classification number: G06N20/00

    Abstract: Techniques are disclosed herein for generating a content item. The techniques include receiving a content item and metadata indicating a level of corruption associated with the content item; and for each iteration included in a plurality of iterations: performing one or more operations to add corruption to a first version of the content item to generate a second version of the content item, and performing one or more operations to reduce corruption in the second version of the content item to generate a third version of the content item, wherein a level of corruption associated with the third version of the content item is less than a level of corruption associated with the first version of the content item.

    HARDWARE SCHEDULING OF ORDERED CRITICAL CODE SECTIONS
    5.
    发明申请
    HARDWARE SCHEDULING OF ORDERED CRITICAL CODE SECTIONS 有权
    硬件安排订购的关键代码段

    公开(公告)号:US20140123150A1

    公开(公告)日:2014-05-01

    申请号:US13660741

    申请日:2012-10-25

    Abstract: One embodiment sets forth a technique for scheduling the execution of ordered critical code sections by multiple threads. A multithreaded processor includes an instruction scheduling unit that is configured to schedule threads to process ordered critical code sections. A ordered critical code section is preceded by a barrier instruction and when all of the threads have reached the barrier instruction, the instruction scheduling unit controls the thread execution order by selecting each thread for execution based on logical identifiers associated with the threads. The logical identifiers are mapped to physical identifiers that are referenced by the multithreaded processor during execution of the threads. The logical identifiers are used by the instruction scheduling unit to control the order in which the threads execute the ordered critical code section.

    Abstract translation: 一个实施例提出了一种用于通过多个线程来调度有序关键代码段的执行的技术。 多线程处理器包括指令调度单元,其被配置为调度线程以处理有序的关键代码段。 有序的关键代码部分之前是屏障指令,并且当所有线程已经到达屏障指令时,指令调度单元通过基于与线程相关联的逻辑标识符选择用于执行的每个线程来控制线程执行顺序。 逻辑标识符被映射到在执行线程期间由多线程处理器引用的物理标识符。 逻辑标识符被指令调度单元用于控制线程执行有序关键代码段的顺序。

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