公开(公告)号：US20240013471A1

公开(公告)日：2024-01-11

申请号：US18471651

申请日：2023-09-21

Applicant: NVIDIA CORPORATION

Inventor： Samuli LAINE ,  Timo AILA ,  Tero KARRAS ,  Gregory MUTHLER ,  William P. NEWHALL, JR. ,  Ronald C. BABICH, JR. ,  Craig KOLB ,  Ignacio LLAMAS ,  John BURGESS

IPC: G06T15/06 ,  G06T15/00 ,  G06T17/00

CPC classification number: G06T15/06 ,  G06T15/005 ,  G06T17/005

Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.

公开(公告)号：US20240303494A1

公开(公告)日：2024-09-12

申请号：US18666613

申请日：2024-05-16

Applicant: NVIDIA Corporation

Inventor： Ming-Yu LIU ,  Xun HUANG ,  Tero Tapani KARRAS ,  Timo AILA ,  Jaakko LEHTINEN

IPC: G06N3/088 ,  G06F18/214 ,  G06F18/2431 ,  G06T3/02 ,  G06T3/60 ,  G06T7/73 ,  G06V10/764 ,  G06V10/82

CPC classification number: G06N3/088 ,  G06F18/214 ,  G06F18/2431 ,  G06T3/02 ,  G06T3/60 ,  G06T7/74 ,  G06V10/764 ,  G06V10/82 ,  G06T2207/20081 ,  G06T2207/20084

Abstract: A few-shot, unsupervised image-to-image translation (“FUNIT”) algorithm is disclosed that accepts as input images of previously-unseen target classes. These target classes are specified at inference time by only a few images, such as a single image or a pair of images, of an object of the target type. A FUNIT network can be trained using a data set containing images of many different object classes, in order to translate images from one class to another class by leveraging few input images of the target class. By learning to extract appearance patterns from the few input images for the translation task, the network learns a generalizable appearance pattern extractor that can be applied to images of unseen classes at translation time for a few-shot image-to-image translation task.

公开(公告)号：US20200302676A1

公开(公告)日：2020-09-24

申请号：US16893107

申请日：2020-06-04

Applicant: NVIDIA CORPORATION

Inventor： Samuli LAINE ,  Timo AILA ,  Tero KARRAS ,  Gregory MUTHLER ,  William P. NEWHALL, JR. ,  Ronald C. BABICH, JR. ,  Craig KOLB ,  Ignacio LLAMAS ,  John BURGESS

IPC: G06T15/06 ,  G06T15/00

Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.

公开(公告)号：US20140123150A1

公开(公告)日：2014-05-01

申请号：US13660741

申请日：2012-10-25

Applicant: NVIDIA CORPORATION

Inventor： John Erik LINDHOLM ,  Tero Tapani KARRAS ,  Samuli Matias LAINE ,  Timo AILA

IPC: G06F9/46

CPC classification number: G06F9/522 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/4881 ,  G06F2209/484

Abstract: One embodiment sets forth a technique for scheduling the execution of ordered critical code sections by multiple threads. A multithreaded processor includes an instruction scheduling unit that is configured to schedule threads to process ordered critical code sections. A ordered critical code section is preceded by a barrier instruction and when all of the threads have reached the barrier instruction, the instruction scheduling unit controls the thread execution order by selecting each thread for execution based on logical identifiers associated with the threads. The logical identifiers are mapped to physical identifiers that are referenced by the multithreaded processor during execution of the threads. The logical identifiers are used by the instruction scheduling unit to control the order in which the threads execute the ordered critical code section.

Abstract translation: 一个实施例提出了一种用于通过多个线程来调度有序关键代码段的执行的技术。 多线程处理器包括指令调度单元，其被配置为调度线程以处理有序的关键代码段。 有序的关键代码部分之前是屏障指令，并且当所有线程已经到达屏障指令时，指令调度单元通过基于与线程相关联的逻辑标识符选择用于执行的每个线程来控制线程执行顺序。 逻辑标识符被映射到在执行线程期间由多线程处理器引用的物理标识符。 逻辑标识符被指令调度单元用于控制线程执行有序关键代码段的顺序。

公开(公告)号：US20240355039A1

公开(公告)日：2024-10-24

申请号：US18761820

申请日：2024-07-02

Applicant: NVIDIA Corporation

Inventor： Samuli LAINE ,  Tero KARRAS ,  Timo AILA ,  Robert OHANNESSIAN ,  William Parsons NEWHALL, Jr. ,  Greg MUTHLER ,  Ian KWONG ,  Peter NELSON ,  John BURGESS

IPC: G06T15/06 ,  G06T15/00

CPC classification number: G06T15/06 ,  G06T15/005

Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.

公开(公告)号：US20220027280A1

公开(公告)日：2022-01-27

申请号：US17483133

申请日：2021-09-23

Applicant: NVIDIA Corporation

Inventor： Greg MUTHLER ,  Timo AILA ,  Tero KARRAS ,  Samuli LAINE ,  William Parsons NEWHALL, JR. ,  Ronald Charles BABICH, JR. ,  John BURGESS ,  Ignacio LLAMAS

IPC: G06F12/0875 ,  G06T15/06 ,  G06F16/901

Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.

公开(公告)号：US20140168238A1

公开(公告)日：2014-06-19

申请号：US13714284

申请日：2012-12-13

Applicant: NVIDIA CORPORATION

Inventor： David LUEBKE ,  Timo AILA ,  Jacopo PANTALEONI ,  David TARJAN

IPC: G06T15/06

CPC classification number: G06T15/06 ,  G06T17/005 ,  G06T2210/52

Abstract: Techniques are disclosed for tracing a ray within a parallel processing unit. A first thread receives a ray or a ray segment for tracing and identifies a first node within an acceleration structure associated with the ray, where the first node is associated with a volume of space traversed by the ray. The thread identifies the child nodes of the first node, where each child node is associated with a different sub-volume of space, and each sub-volume is associated with a corresponding ray segment. The thread determines that two or more nodes are associated with sub-volumes of space that intersect the ray segment. The thread selects one of these nodes for processing by the first thread and another for processing by a second thread. One advantage of the disclosed technique is that the threads in a thread group perform ray tracing more efficiently in that idle time is reduced.

公开(公告)号：US20200051315A1

公开(公告)日：2020-02-13

申请号：US16101180

申请日：2018-08-10

Applicant: NVIDIA Corporation

Inventor： Samuli Laine ,  Timo AILA ,  Tero KARRAS ,  Gregory MUTHLER ,  William Parsons NEWHALL, JR. ,  Ronald Charles BABICH, JR. ,  Craig KOLB ,  Ignacio LLAMAS

IPC: G06T15/06 ,  G06T7/60 ,  G06T15/60 ,  G06F17/30

Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.

公开(公告)号：US20200050550A1

公开(公告)日：2020-02-13

申请号：US16101109

申请日：2018-08-10

Applicant: NVIDIA Corporation

Inventor： Greg MUTHLER ,  Timo AILA ,  Tero KARRAS ,  Samuli LAINE ,  William Parsons NEWHALL ,  Ronald Charles BABICH ,  John BURGESS ,  Ignacio LLAMAS

IPC: G06F12/0875 ,  G06T15/06 ,  G06F17/30

Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.

公开(公告)号：US20140168228A1

公开(公告)日：2014-06-19

申请号：US13714287

申请日：2012-12-13

Applicant: NVIDIA CORPORATION

Inventor： David LUEBKE ,  Timo AILA ,  Jacopo PANTALEONI ,  David TARJAN

IPC: G06F9/38

CPC classification number: G06F9/5066 ,  G06T15/06

Abstract: Techniques are disclosed for tracing a ray within a parallel processing unit. A first thread receives a ray or a ray segment for tracing and identifies a first node within an acceleration structure associated with the ray, where the first node is associated with a volume of space traversed by the ray. The thread identifies the child nodes of the first node, where each child node is associated with a different sub-volume of space, and each sub-volume is associated with a corresponding ray segment. The thread determines that two or more nodes are associated with sub-volumes of space that intersect the ray segment. The thread selects one of these nodes for processing by the first thread and another for processing by a second thread. One advantage of the disclosed technique is that the threads in a thread group perform ray tracing more efficiently in that idle time is reduced.

Abstract translation: 公开了用于跟踪并行处理单元内的射线的技术。 第一线程接收用于跟踪的射线或射线段，并识别与射线相关联的加速结构内的第一节点，其中第一节点与由射线穿过的空间体积相关联。 该线程标识第一节点的子节点，其中每个子节点与不同的子体积的空间相关联，并且每个子卷与相应的射线段相关联。 线程确定两个或多个节点与与射线段相交的空间的子卷相关联。 线程选择其中一个节点进行第一个线程处理，另一个线程由第二个线程进行处理。 所公开技术的一个优点是螺纹组中的螺纹更有效地执行光线追踪，从而减少了空闲时间。