公开(公告)号：US20230153510A1

公开(公告)日：2023-05-18

申请号：US17738174

申请日：2022-05-06

Applicant: NVIDIA Corporation

Inventor： Haoyu Yang ,  Haoxing Ren ,  Zongyi Li

IPC: G06F30/398 ,  G06F30/27 ,  G06F17/14

CPC classification number: G06F30/398 ,  G06F30/27 ,  G06F17/142 ,  G06F2119/18

Abstract: As integrated circuit geometries have shrunk, lithography simulation has developed to ensure that the masks used to fabricate the circuits satisfy the chip yield and fabrication turnaround time targets. To manufacture an integrated circuit (chip), an initial layout for the integrated circuit design is processed to compute a wafer image (e.g., resist material “printed” on the wafer using photomasks). Lithography simulation processes the initial layout according to optical physics to compute an estimated wafer image without actually constructing the physical masks or consuming any wafer fabrication resources and may be used to confirm manufacturability of the design layout before it is fabricated. Performing lithography simulation using a dual-band neural network produces accurate results efficiently. Dual-band refers to a dual frequency band processing whereby the input layout (mask image) is separately processed by both a first and second branch to extract low-frequency (global) features and high-frequency (local) features, respectively.

公开(公告)号：US20240256753A1

公开(公告)日：2024-08-01

申请号：US18605355

申请日：2024-03-14

Applicant: NVIDIA Corporation

Inventor： Shaurakar Das ,  Haoxing Ren ,  Santosh Santosh ,  SeshasaiJyothi Kolli ,  Muhammad Arif Mirza ,  Sreedhar Pratty

IPC: G06F30/392 ,  G06F30/398 ,  H01L27/02

CPC classification number: G06F30/392 ,  G06F30/398 ,  H01L27/0207

Abstract: To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops.

公开(公告)号：US12045307B2

公开(公告)日：2024-07-23

申请号：US17086118

申请日：2020-10-30

Applicant: NVIDIA Corporation

Inventor： Brucek Kurdo Khailany ,  Steve Haihang Dai ,  Rangharajan Venkatesan ,  Haoxing Ren

IPC: G06F17/16 ,  G06F5/01 ,  G06F7/544

CPC classification number: G06F17/16 ,  G06F5/01 ,  G06F7/5443

Abstract: Today neural networks are used to enable autonomous vehicles and improve the quality of speech recognition, real-time language translation, and online search optimizations. However, operation of the neural networks for these applications consumes energy. Quantization of parameters used by the neural networks reduces the amount of memory needed to store the parameters while also reducing the power consumed during operation of the neural network. Matrix operations performed by the neural networks require many multiplication calculations, so reducing the number of bits that are multiplied reduces the energy that is consumed. Quantizing smaller sets of the parameters using a shared scale factor improves accuracy compared with quantizing larger sets of the parameters. Accuracy of the calculations may be maintained by quantizing and scaling the parameters using fine-grained per-vector scale factors. A vector includes one or more elements within a single dimension of a multi-dimensional matrix.

公开(公告)号：US20240168390A1

公开(公告)日：2024-05-23

申请号：US18232757

申请日：2023-08-10

Applicant: NVIDIA Corporation

Inventor： Haoyu Yang ,  Haoxing Ren

IPC: G03F7/00 ,  G06T7/00

CPC classification number: G03F7/706841 ,  G03F7/70683 ,  G06T7/0006 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2207/30148

Abstract: In the semiconductor industry, lithography refers to a manufacturing process in which light is projected through a geometric design on a mask to illuminate the design on a semiconductor wafer. The wafer has a light-sensitive material (i.e. resist) on its surface which, when illuminated by the light, causes the design to be etched onto the wafer. However, this lithography process does not perfectly transfer the design to the wafer, particularly because some diffracted light will inevitably distort the pattern etched onto the wafer (i.e. the resist image). To address this issue in lithography, an inverse lithography technology has been developed which optimizes the mask to match the desired shapes on the wafer. The present disclosure improves current inverse lithography technology by employing machine learning for mask optimization.

公开(公告)号：US12277376B2

公开(公告)日：2025-04-15

申请号：US18605355

申请日：2024-03-14

Applicant: NVIDIA Corporation

Inventor： Shaurakar Das ,  Haoxing Ren ,  Santosh Santosh ,  SeshasaiJyothi Kolli ,  Muhammad Arif Mirza ,  Sreedhar Pratty

IPC: G06F30/392 ,  G06F30/398 ,  H10D89/10

Abstract: To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops.

公开(公告)号：US20230089606A1

公开(公告)日：2023-03-23

申请号：US17540167

申请日：2021-12-01

Applicant: NVIDIA Corporation

Inventor： Vidya Chhabria ,  Benjamin Andrew Keller ,  Yanqing Zhang ,  Brucek Kurdo Khailany ,  Haoxing Ren

IPC: G06F30/3312 ,  G06F30/27 ,  G06N20/00

Abstract: To facilitate crosstalk analysis for an IC design, a plurality of input vectors are input into a gate-level simulation. In response, the gate-level simulation determines timing windows for all nets within the IC design, may perform aggressor pruning, and may then determine and output aggressor/victim pairs and associated features for the IC design. This gate-level simulation may be accelerated utilizing one or more graphics processor units (GPUs). Additionally, the aggressor/victim pairs and associated features for the IC design are then input into a trained machine learning environment, which outputs predicted delta delays for each of the aggressor/victim pairs. In this way, crosstalk analysis may be performed more accurately and efficiently.

公开(公告)号：US20220067481A1

公开(公告)日：2022-03-03

申请号：US17211695

申请日：2021-03-24

Applicant: NVIDIA Corporation

Inventor： Vidya Chhabria ,  Yanqing Zhang ,  Haoxing Ren ,  Brucek Kurdo Khailany

IPC: G06N3/04 ,  G06N3/08 ,  G06F30/36

Abstract: The IR drop for a portion of a circuit may include a voltage drop across resistance, and may include a product of current I passing through resistance with a resistance value R. In order to determine IR drop for a circuit in a more accurate and efficient manner, a neural network produces coefficient maps (that each indicate a time-varying distribution of power within an associated portion of the circuit), and these coefficient maps are then used by the neural network to determine an IR drop for each of a plurality of portions of the circuit.

公开(公告)号：US12019967B2

公开(公告)日：2024-06-25

申请号：US17230016

申请日：2021-04-14

Applicant: Nvidia Corporation

Inventor： Haoxing Ren ,  Matthew Fojtik

IPC: G06N3/04 ,  G06F30/27 ,  G06F30/394 ,  G06N3/08

CPC classification number: G06F30/394 ,  G06N3/04 ,  G06N3/08

Abstract: The disclosure provides a general solution for determining connections between terminals of various types of circuits using machine learning (ML). A ML method that uses reinforcement learning (RL), such as deep RL, to determine and optimize routing of circuit connections using a game process is provided. In one example a method of determining routing connection includes: (1) receiving a circuit design having known terminal groups, (2) establishing terminal positions for the terminal groups in a routing environment, and (3) determining, by the RL agent, routes of nets between the known terminal groups employing a model that is independent of a number of the nets of the circuit. A method of creating a model for routing nets using RL, a method of employing a game for training a RL agent to determine routing connections, and a RL agent for routing connections of a circuit are also disclosed.

公开(公告)号：US20220067512A1

公开(公告)日：2022-03-03

申请号：US17086114

申请日：2020-10-30

Applicant: NVIDIA Corporation

Inventor： Brucek Kurdo Khailany ,  Steve Haihang Dai ,  Rangharajan Venkatesan ,  Haoxing Ren

IPC: G06N3/08 ,  G06N3/04 ,  G06F17/16

Abstract: Today neural networks are used to enable autonomous vehicles and improve the quality of speech recognition, real-time language translation, and online search optimizations. However, operation of the neural networks for these applications consumes energy. Quantization of parameters used by the neural networks reduces the amount of memory needed to store the parameters while also reducing the power consumed during operation of the neural network. Matrix operations performed by the neural networks require many multiplication calculations, so reducing the number of bits that are multiplied reduces the energy that is consumed. Quantizing smaller sets of the parameters using a shared scale factor improves accuracy compared with quantizing larger sets of the parameters. Accuracy of the calculations may be maintained by quantizing and scaling the parameters using fine-grained per-vector scale factors. A vector includes one or more elements within a single dimension of a multi-dimensional matrix.

公开(公告)号：US11972188B2

公开(公告)日：2024-04-30

申请号：US17505374

申请日：2021-10-19

Applicant: NVIDIA Corporation

Inventor： Shaurakar Das ,  Haoxing Ren ,  Santosh Santosh ,  SeshasaiJyothi Kolli ,  Muhammad Arif Mirza ,  Sreedhar Pratty

IPC: G06F30/392 ,  G06F30/398 ,  H01L27/02

CPC classification number: G06F30/392 ,  G06F30/398 ,  H01L27/0207

Abstract: To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops.