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公开(公告)号：US11886885B2
公开(公告)日：2024-01-30
申请号：US17480728
申请日：2021-09-21
Applicant: NVIDIA CORPORATION
Inventor： Benjamin Andrew Keller
CPC classification number: G06F9/3869 , G06F5/16 , G06F13/1642 , G11C7/1063 , H03K19/20
Abstract: One embodiment of the present invention sets forth a data pipeline, which includes a first mousetrap element and a second mousetrap element in a first pipeline stage. Each mousetrap element includes a request latch that, when enabled, allows a request signal to pass from the first pipeline stage to a second pipeline stage following the first pipeline stage in the data pipeline. Each mousetrap element also includes a data latch that, when enabled, allows a data element to pass from the first pipeline stage to the second pipeline stage. Each mousetrap element further includes a latch controller that enables and disables the request and data latches based on a phase signal that alternates between a first value that configures the first mousetrap element to transmit data to the second pipeline stage and a second value that configures the second mousetrap element to transmit data to the second pipeline stage.
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公开(公告)号：US20160148661A1
公开(公告)日：2016-05-26
申请号：US14948175
申请日：2015-11-20
Applicant: NVIDIA Corporation
CPC classification number: G06F5/06 , G06F2205/061 , G11C7/222 , G11C8/16 , G11C2207/2254 , G11C2207/2272
Abstract: A system, method, and computer program product are provided for a pausible bisynchronous FIFO. Data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array and an increment signal is generated in the first clock domain. The increment signal is determined to transition near an edge of a second dock signal, where the second clock signal is a pausible clock signal. A next edge of the second clock signal of the second clock domain is delayed and the increment signal to the second clock domain and is transmitted.
Abstract translation: 提供了一种用于可暂存双工FIFO的系统，方法和计算机程序产品。 将数据与第一时钟域的第一时钟信号同步地写入双端口存储器阵列的条目，并且在第一时钟域中生成增量信号。 增量信号被确定为在第二对接信号的边缘附近转变，其中第二时钟信号是可暂停的时钟信号。 第二时钟域的第二时钟信号的下一个边缘被延迟，并且将增量信号发送到第二时钟域并被发送。
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公开(公告)号：US20230089606A1
公开(公告)日：2023-03-23
申请号：US17540167
申请日：2021-12-01
Applicant: NVIDIA Corporation
Inventor： Vidya Chhabria , Benjamin Andrew Keller , Yanqing Zhang , Brucek Kurdo Khailany , Haoxing Ren
IPC: G06F30/3312 , G06F30/27 , G06N20/00
Abstract: To facilitate crosstalk analysis for an IC design, a plurality of input vectors are input into a gate-level simulation. In response, the gate-level simulation determines timing windows for all nets within the IC design, may perform aggressor pruning, and may then determine and output aggressor/victim pairs and associated features for the IC design. This gate-level simulation may be accelerated utilizing one or more graphics processor units (GPUs). Additionally, the aggressor/victim pairs and associated features for the IC design are then input into a trained machine learning environment, which outputs predicted delta delays for each of the aggressor/victim pairs. In this way, crosstalk analysis may be performed more accurately and efficiently.
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公开(公告)号：US09672008B2
公开(公告)日：2017-06-06
申请号：US14948175
申请日：2015-11-20
Applicant: NVIDIA Corporation
CPC classification number: G06F5/06 , G06F2205/061 , G11C7/222 , G11C8/16 , G11C2207/2254 , G11C2207/2272
Abstract: A system, method, and computer program product are provided for a pausible bisynchronous FIFO. Data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array and an increment signal is generated in the first clock domain. The increment signal is determined to transition near an edge of a second dock signal, where the second clock signal is a pausible clock signal. A next edge of the second clock signal of the second clock domain is delayed and the increment signal to the second clock domain and is transmitted.
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