公开(公告)号：US20240036957A1

公开(公告)日：2024-02-01

申请号：US17955175

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/54

CPC classification number: G06F9/544 ,  G06F9/545

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to cause memory to be shared between two or more groups of blocks of threads.

公开(公告)号：US20240036955A1

公开(公告)日：2024-02-01

申请号：US17955133

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/54 ,  G06F9/48

CPC classification number: G06F9/544 ,  G06F9/4881

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads.

公开(公告)号：US20240036916A1

公开(公告)日：2024-02-01

申请号：US17955094

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/545 ,  G06F9/5044

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate a maximum number of blocks of threads capable of being scheduled in parallel.

公开(公告)号：US20240036915A1

公开(公告)日：2024-02-01

申请号：US17955070

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/505

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to determine a scheduling policy of one or more blocks of one or more threads.

公开(公告)号：US20220365750A1

公开(公告)日：2022-11-17

申请号：US17745512

申请日：2022-05-16

Applicant: NVIDIA Corporation

Inventor： Girish Bhaskarrao Bharambe ,  Kyrylo Perelygin ,  Advait Soman ,  Andrew Robert Kerr ,  Farhana Schuchman ,  Jaydeep Marathe ,  Stephen Anthony Bernard Jones ,  Ronny Meir Krashinsky ,  Jaewook Shin

IPC: G06F7/499 ,  G06F7/485 ,  G06F7/544 ,  G06F17/16

Abstract: Apparatuses, systems, and techniques to generate numbers. In at least one embodiment, one or more circuits are to cause one or more thirty-two bit floating point numbers to be truncated to generate one or more rounded numbers based, at least in part, on one or more rounding attributes.

公开(公告)号：US09483235B2

公开(公告)日：2016-11-01

申请号：US13850207

申请日：2013-03-25

Applicant: NVIDIA Corporation

Inventor： Michael Murphy ,  Sean Y. Lee ,  Stephen Jones ,  Girish Bharambe ,  Jaydeep Marathe

IPC: G06F9/45 ,  G06F9/44 ,  G06F9/445

CPC classification number: G06F8/30 ,  G06F8/41 ,  G06F8/54

Abstract: Embodiments of the present invention provide a novel solution that supports the separate compilation of host code and device code used within a heterogeneous programming environment. Embodiments of the present invention are operable to link device code embedded within multiple host object files using a separate device linking operation. Embodiments of the present invention may extract device code from their respective host object files and then linked them together to form linked device code. This linked device code may then be embedded back into a host object generated by embodiments of the present invention which may then be passed to a host linker to form a host executable file. As such, device code may be split into multiple files and then linked together to form a final executable file by embodiments of the present invention.

Abstract translation: 本发明的实施例提供了一种新颖的解决方案，其支持在异构编程环境中使用的主机代码和设备代码的单独编译。 本发明的实施例可操作以使用单独的设备链接操作链接嵌入在多个主机对象文件内的设备代码。 本发明的实施例可以从其各自的主机对象文件中提取设备代码，然后将它们链接在一起以形成链接的设备代码。 然后将该链接的设备代码嵌入到由本发明的实施例生成的主机对象中，然后可以将其传递到主机链接器以形成主机可执行文件。 因此，设备代码可以被分割成多个文件，然后通过本发明的实施例链接在一起以形成最终的可执行文件。

公开(公告)号：US20240036945A1

公开(公告)日：2024-02-01

申请号：US17955153

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/52 ,  G06F9/54

CPC classification number: G06F9/522 ,  G06F9/545

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction.

公开(公告)号：US20240036944A1

公开(公告)日：2024-02-01

申请号：US17955143

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/52 ,  G06F9/54

CPC classification number: G06F9/522 ,  G06F9/545

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction.

公开(公告)号：US20220365882A1

公开(公告)日：2022-11-17

申请号：US17395255

申请日：2021-08-05

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Luke David Durant ,  Stephen Jones ,  Jack H. Choquette ,  Ronny Krashinsky ,  Dmitri Vainbrand ,  Olivier Giroux ,  Olivier Francois Joseph Harel ,  Shirish Gadre ,  Ze Long ,  Matthieu Tardy ,  David Dastous St Hilaire ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Jaewook Shin ,  Jayashree Venkatesh ,  Girish Bhaskar Bharambe

IPC: G06F12/0895

Abstract: Apparatuses, systems, and techniques to control operation of a memory cache. In at least one embodiment, cache guidance is specified within application source code by associating guidance with declaration of a memory block, and then applying specified guidance to source code statements that access said memory block.

公开(公告)号：US20190196797A1

公开(公告)日：2019-06-27

申请号：US16287392

申请日：2019-02-27

Applicant: Nvidia Corporation

Inventor： Jaydeep Marathe ,  Vinod Grover

IPC: G06F8/41

CPC classification number: G06F8/41 ,  G06F8/51

Abstract: A system and method for processing source code for compilation. The method includes accessing a portion of host source code and determining whether the portion of the host source code comprises a device lambda expression. The method further includes in response to the portion of host code comprising the device lambda expression, determining a unique placeholder type instantiation based on the device lambda expression and modifying the device lambda expression based on the unique placeholder type instantiation to produce modified host source code. The method further includes sending the modified host source code to a host compiler.