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1.发明申请公开(公告)号：US20220392148A1
公开(公告)日：2022-12-08
申请号：US17889545
申请日：2022-08-17
申请人： NVIDIA Corporation
发明人： Greg Muthler , Ronald Charles Babich, JR. , William Parsons Newhall, JR. , Peter Nelson , James Robertson , John Burgess
摘要： In a ray tracer, to prevent any long-running query from hanging the graphics processing unit, a traversal coprocessor provides a preemption mechanism that will allow rays to stop processing or time out early. The example non-limiting implementations described herein provide such a preemption mechanism, including a forward progress guarantee, and additional programmable timeout options that can be time or cycle based. Those programmable options provide a means for quality of service timing guarantees for applications such as virtual reality (VR) that have strict timing requirements.
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公开(公告)号：US11328472B2
公开(公告)日：2022-05-10
申请号：US17032818
申请日：2020-09-25
申请人： NVIDIA Corporation
发明人： Samuli Laine , Tero Karras , Timo Aila , Robert Ohannessian , William Parsons Newhall, Jr. , Greg Muthler , Ian Kwong , Peter Nelson , John Burgess
摘要： A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.
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公开(公告)号：US10825230B2
公开(公告)日：2020-11-03
申请号：US16101148
申请日：2018-08-10
申请人： NVIDIA Corporation
发明人： Samuli Laine , Tero Karras , Timo Aila , Robert Ohannessian , William Parsons Newhall, Jr. , Greg Muthler , Ian Kwong , Peter Nelson , John Burgess
摘要： A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.
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公开(公告)号：US11704863B2
公开(公告)日：2023-07-18
申请号：US17716599
申请日：2022-04-08
申请人： NVIDIA Corporation
发明人： Samuli Laine , Tero Karras , Timo Aila , Robert Ohannessian , William Parsons Newhall, Jr. , Greg Muthler , Ian Kwong , Peter Nelson , John Burgess
CPC分类号： G06T15/06 , G06T15/005
摘要： A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.
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5.发明授权公开(公告)号：US11455768B2
公开(公告)日：2022-09-27
申请号：US17111844
申请日：2020-12-04
申请人： NVIDIA Corporation
发明人： Greg Muthler , Ronald Charles Babich, Jr. , William Parsons Newhall, Jr. , Peter Nelson , James Robertson , John Burgess
摘要： In a ray tracer, to prevent any long-running query from hanging the graphics processing unit, a traversal coprocessor provides a preemption mechanism that will allow rays to stop processing or time out early. The example non-limiting implementations described herein provide such a preemption mechanism, including a forward progress guarantee, and additional programmable timeout options that can be time or cycle based. Those programmable options provide a means for quality of service timing guarantees for applications such as virtual reality (VR) that have strict timing requirements.
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公开(公告)号：US10810785B2
公开(公告)日：2020-10-20
申请号：US16101206
申请日：2018-08-10
申请人： NVIDIA Corporation
发明人： Greg Muthler , Ronald Charles Babich, Jr. , William Parsons Newhall, Jr. , Peter Nelson , James Robertson , John Burgess
摘要： In a ray tracer, to prevent any long-running query from hanging the graphics processing unit, a traversal coprocessor provides a preemption mechanism that will allow rays to stop processing or time out early. The example non-limiting implementations described herein provide such a preemption mechanism, including a forward progress guarantee, and additional programmable timeout options that can be time or cycle based. Those programmable options provide a means for quality of service timing guarantees for applications such as virtual reality (VR) that have strict timing requirements.
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公开(公告)号：US20200034143A1
公开(公告)日：2020-01-30
申请号：US16595398
申请日：2019-10-07
申请人： NVIDIA Corporation
摘要： In one embodiment, a synchronization instruction causes a processor to ensure that specified threads included within a warp concurrently execute a single subsequent instruction. The specified threads include at least a first thread and a second thread. In operation, the first thread arrives at the synchronization instruction. The processor determines that the second thread has not yet arrived at the synchronization instruction and configures the first thread to stop executing instructions. After issuing at least one instruction for the second thread, the processor determines that all the specified threads have arrived at the synchronization instruction. The processor then causes all the specified threads to execute the subsequent instruction. Advantageously, unlike conventional approaches to synchronizing threads, the synchronization instruction enables the processor to reliably and properly execute code that includes complex control flows and/or instructions that presuppose that threads are converged.
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公开(公告)号：US12067669B2
公开(公告)日：2024-08-20
申请号：US18198949
申请日：2023-05-18
申请人： NVIDIA Corporation
发明人： Samuli Laine , Tero Karras , Timo Aila , Robert Ohannessian , William Parsons Newhall, Jr. , Greg Muthler , Ian Kwong , Peter Nelson , John Burgess
CPC分类号： G06T15/06 , G06T15/005
摘要： A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.
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9.发明授权公开(公告)号：US11928772B2
公开(公告)日：2024-03-12
申请号：US17889545
申请日：2022-08-17
申请人： NVIDIA Corporation
发明人： Greg Muthler , Ronald Charles Babich, Jr. , William Parsons Newhall, Jr. , Peter Nelson , James Robertson , John Burgess
CPC分类号： G06T15/06 , G06F9/3877 , G06N5/046 , G06T1/20 , G06T1/60 , G06T17/005
摘要： In a ray tracer, to prevent any long-running query from hanging the graphics processing unit, a traversal coprocessor provides a preemption mechanism that will allow rays to stop processing or time out early. The example non-limiting implementations described herein provide such a preemption mechanism, including a forward progress guarantee, and additional programmable timeout options that can be time or cycle based. Those programmable options provide a means for quality of service timing guarantees for applications such as virtual reality (VR) that have strict timing requirements.
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公开(公告)号：US20180314520A1
公开(公告)日：2018-11-01
申请号：US15499843
申请日：2017-04-27
申请人： NVIDIA Corporation
CPC分类号： G06F9/3009 , G06F9/30087 , G06F9/3851 , G06F9/46
摘要： In one embodiment, a synchronization instruction causes a processor to ensure that specified threads included within a warp concurrently execute a single subsequent instruction. The specified threads include at least a first thread and a second thread. In operation, the first thread arrives at the synchronization instruction. The processor determines that the second thread has not yet arrived at the synchronization instruction and configures the first thread to stop executing instructions. After issuing at least one instruction for the second thread, the processor determines that all the specified threads have arrived at the synchronization instruction. The processor then causes all the specified threads to execute the subsequent instruction. Advantageously, unlike conventional approaches to synchronizing threads, the synchronization instruction enables the processor to reliably and properly execute code that includes complex control flows and/or instructions that presuppose that threads are converged.
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