公开(公告)号：US10826511B1

公开(公告)日：2020-11-03

申请号：US16785495

申请日：2020-02-07

Applicant: NXP B.V.

Inventor： Sushil Kumar Gupta ,  Pankaj Agrawal ,  Ashish Panpalia

IPC: H03M1/38 ,  H03M1/06

Abstract: A pipeline analog-to-digital converter (ADC) includes a hybrid multiplying digital-to-analog converter (MDAC) that includes multiple digital-to-analog converters (DACs), an amplifier, and a conversion circuit. The multiple DACs function in a pipelined manner such that each DAC receives an analog input signal in different cycles of a clock signal and generates a corresponding analog output signal. The amplifier amplifies each analog output signal to generate a corresponding amplified analog signal in different cycles of the clock signal. The conversion circuit successively approximates each analog output signal to generate multiple digital signals. Thus, a digital output signal of the pipeline ADC is generated based on the corresponding amplified analog signal and at least one of the multiple digital signals. The pipeline ADC utilizes one cycle for performing each of sampling, conversion, and amplification operations, which results into low power consumption by the pipeline ADC.

公开(公告)号：US11018684B1

公开(公告)日：2021-05-25

申请号：US17005076

申请日：2020-08-27

Applicant: NXP B.V.

Inventor： Sushil Kumar Gupta ,  Pankaj Agrawal ,  Ashish Panpalia

IPC: H03M1/46 ,  H03M1/74 ,  H03M1/68 ,  H03M1/12

Abstract: A pipeline analog-to-digital converter (ADC) includes a hybrid multiplying digital-to-analog converter (MDAC) that includes multiple digital-to-analog converters (DACs), at least one conversion circuit, and at least one amplifier such that a number of conversion circuits and a number of amplifiers is less than a number of DACs. Each DAC is configured to receive an analog input signal in non-overlapping durations of a clock signal and generate a corresponding analog output signal. At least one of the conversion circuits is coupled with at least two DACs, and each conversion circuit is configured to perform conversion operation on a corresponding analog output signal to generate digital signals. At least one of the amplifiers is coupled with at least two DACs, and each amplifier is configured to perform amplification operation on a corresponding analog output signal.

公开(公告)号：US11018682B1

公开(公告)日：2021-05-25

申请号：US16886474

申请日：2020-05-28

Applicant: NXP B.V.

Inventor： Sushil Kumar Gupta ,  Pankaj Agrawal ,  Ashish Panpalia

IPC: H03M1/12 ,  H03M1/14 ,  H03M1/46

Abstract: A sub-ranging analog-to-digital converter (ADC) includes a coarse ADC and a fine ADC that receives a set of coarse signals from the coarse ADC. The fine ADC includes multiple digital-to-analog converters (DACs) and multiple converters such that a number of converters is less than a number of DACs. The DACs and the converters function in a partial time-interleaved manner where each DAC receives an analog input signal in different non-overlapping durations of a clock signal and generates a corresponding analog output signal. At least one of the converters is coupled with at least two DACs, and each converter is configured to receive the corresponding analog output signals and perform conversion operation to generate digital signals in non-overlapping durations of the clock signal, respectively. The durations for performing conversion operation of at least two of the converters overlap partially.