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公开(公告)号：US11449088B2
公开(公告)日：2022-09-20
申请号：US17248849
申请日：2021-02-10
Applicant: NXP B.V.
Inventor： Sushil Kumar Gupta , Mukul Pancholi
Abstract: A bandgap reference voltage generator can include a bandgap core circuit configured to output at least one control voltage. The bandgap reference voltage generator can further include feedback circuitry that can be configured to receive a control voltage outputted by the bandgap core circuit or another control voltage generated based on the control voltage, and output a current. The current can be outputted such that the current is sourced to or sank from the bandgap core circuit. The feedback circuitry can be further configured to generate a bandgap reference voltage. When the current is sourced to the bandgap core circuit, the bandgap reference voltage can be greater than a threshold value. Similarly, when the current is sank from the bandgap core circuit, the bandgap reference voltage can be less than the threshold value.
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公开(公告)号：US10438677B1
公开(公告)日：2019-10-08
申请号：US16197290
申请日：2018-11-20
Applicant: NXP B.V.
Inventor： Sushil Kumar Gupta , Hitesh Kumar Garg
Abstract: A sample-and-hold circuit is broken down into multiple parallel modules, and an output switch, where each module includes a switch and a capacitor. Each of the switches in the modules and the output switch are controlled by different phases of a clock signal. The sample-and-hold circuit receives an input signal and operates in sample and hold modes to generate a sampled output signal.
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公开(公告)号：US11669116B2
公开(公告)日：2023-06-06
申请号：US17304636
申请日：2021-06-23
Applicant: NXP B.V.
Inventor： Sushil Kumar Gupta , Pankaj Agrawal
IPC: G05F1/575
CPC classification number: G05F1/575
Abstract: A low dropout regulator includes a proportional-to-absolute-temperature (PTAT) circuit, an amplification circuit, and an output circuit. The PTAT circuit outputs one current, and the amplification circuit outputs one or more currents. The one or more currents are outputted by the amplification circuit based on collector-emitter voltages associated with transistors of the PTAT circuit. Alternatively, the one or more currents are outputted by the amplification circuit based on the current outputted by the PTAT circuit and the collector-emitter voltages associated with the transistors of the PTAT circuit. The output circuit generates one or more output voltages based on at least one of a base-emitter voltage associated with a transistor of the PTAT circuit and a current of the one or more currents outputted by the amplification circuit.
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公开(公告)号：US11520364B2
公开(公告)日：2022-12-06
申请号：US17247257
申请日：2020-12-04
Applicant: NXP B.V.
Inventor： Koteswararao Nannapaneni , Sushil Kumar Gupta
Abstract: An electronic system comprising a voltage-to-current converter and a proportional-to-absolute-temperature (PTAT) circuit is disclosed. The voltage-to-current converter is configured to receive one of a control voltage, a supply voltage, a scaled-down version of the control voltage, and a scaled-down version of the supply voltage, and generate a set of currents. The PTAT circuit is coupled with the voltage-to-current converter such that each current of the set of currents is one of sourced to the PTAT circuit and sank from the PTAT circuit. Further, the PTAT circuit is configured to receive at least one of the supply voltage and the control voltage, and generate a set of reference voltages. The control voltage is generated based on the set of reference voltages and the supply voltage.
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公开(公告)号：US20210408975A1
公开(公告)日：2021-12-30
申请号：US16917604
申请日：2020-06-30
Applicant: NXP B.V.
Inventor： Sushil Kumar Gupta
IPC: H03F3/00
Abstract: A switched-capacitor amplifier circuit includes multiple switched-capacitor networks, an amplifier, and multiple reset circuits. The switched-capacitor networks are configured to receive respective input voltages during a sampling phase, and generate sampled voltages. During an amplification phase, the amplifier is coupled with the switched-capacitor networks, and is configured to receive the sampled voltages. The amplifier is further configured to generate output voltages. During the sampling phase, the amplifier is coupled with the reset circuits, and is further configured to receive divided voltages such that the amplifier is reset. The reset circuits are configured to receive and provide a common-mode voltage and the output voltages to the amplifier. The divided voltages are generated based on the common-mode voltage and the output voltages. Each reset circuit includes at least one of a resistor and a capacitor.
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Patent Agency Ranking
公开(公告)号：US20220413532A1
公开(公告)日：2022-12-29
申请号：US17304636
申请日：2021-06-23
Applicant: NXP B.V.
Inventor： Sushil Kumar Gupta , Pankaj Agrawal
IPC: G05F1/575
Abstract: A low dropout regulator includes a proportional-to-absolute-temperature (PTAT) circuit, an amplification circuit, and an output circuit. The PTAT circuit outputs one current, and the amplification circuit outputs one or more currents. The one or more currents are outputted by the amplification circuit based on collector-emitter voltages associated with transistors of the PTAT circuit. Alternatively, the one or more currents are outputted by the amplification circuit based on the current outputted by the PTAT circuit and the collector-emitter voltages associated with the transistors of the PTAT circuit. The output circuit generates one or more output voltages based on at least one of a base-emitter voltage associated with a transistor of the PTAT circuit and a current of the one or more currents outputted by the amplification circuit.
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公开(公告)号：US11449087B1
公开(公告)日：2022-09-20
申请号：US17454646
申请日：2021-11-12
Applicant: NXP B.V.
Inventor： Sushil Kumar Gupta
Abstract: An integrated circuit (IC) includes a self-biased circuit and a start-up circuit for the self-biased circuit. The self-biased circuit generates a start-up indicator signal and an output signal. The start-up indicator signal indicates whether the self-biased circuit has started up. The start-up circuit includes a comparator, a start-up controller, and a peak controller. The comparator compares the start-up indicator signal with a reference signal generated based on supply voltages, and generates a comparison signal. The start-up controller controls a start-up of the self-biased circuit when the comparison signal is at a first logic state. Further, when the comparison signal transitions from the first logic state to a second logic state, the peak controller controls the output signal to maintain one of a voltage level and a current level of the output signal below a peak limit.
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公开(公告)号：US11211904B1
公开(公告)日：2021-12-28
申请号：US16917604
申请日：2020-06-30
Applicant: NXP B.V.
Inventor： Sushil Kumar Gupta
Abstract: A switched-capacitor amplifier circuit includes multiple switched-capacitor networks, an amplifier, and multiple reset circuits. The switched-capacitor networks are configured to receive respective input voltages during a sampling phase, and generate sampled voltages. During an amplification phase, the amplifier is coupled with the switched-capacitor networks, and is configured to receive the sampled voltages. The amplifier is further configured to generate output voltages. During the sampling phase, the amplifier is coupled with the reset circuits, and is further configured to receive divided voltages such that the amplifier is reset. The reset circuits are configured to receive and provide a common-mode voltage and the output voltages to the amplifier. The divided voltages are generated based on the common-mode voltage and the output voltages. Each reset circuit includes at least one of a resistor and a capacitor.
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公开(公告)号：US10826511B1
公开(公告)日：2020-11-03
申请号：US16785495
申请日：2020-02-07
Applicant: NXP B.V.
Inventor： Sushil Kumar Gupta , Pankaj Agrawal , Ashish Panpalia
Abstract: A pipeline analog-to-digital converter (ADC) includes a hybrid multiplying digital-to-analog converter (MDAC) that includes multiple digital-to-analog converters (DACs), an amplifier, and a conversion circuit. The multiple DACs function in a pipelined manner such that each DAC receives an analog input signal in different cycles of a clock signal and generates a corresponding analog output signal. The amplifier amplifies each analog output signal to generate a corresponding amplified analog signal in different cycles of the clock signal. The conversion circuit successively approximates each analog output signal to generate multiple digital signals. Thus, a digital output signal of the pipeline ADC is generated based on the corresponding amplified analog signal and at least one of the multiple digital signals. The pipeline ADC utilizes one cycle for performing each of sampling, conversion, and amplification operations, which results into low power consumption by the pipeline ADC.
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公开(公告)号：US20240137034A1
公开(公告)日：2024-04-25
申请号：US18296741
申请日：2023-04-06
Applicant: NXP B.V.
Inventor： Sushil Kumar Gupta , Kamlesh Singh
IPC: H03M1/10
CPC classification number: H03M1/1014
Abstract: A time-interleaved analog to digital converter (ADC) circuit includes an input signal amplitude detector configured to determine an input signal amplitude of an analog input signal, a multi-tone signal generator configured to generate a plurality of analog and digital sinusoidal signals having an amplitude dependent on the determined input signal amplitude, and an analog input summing module configured to provide a summed output analog signal from the analog input signal and the analog sinusoidal signals. A time-interleaved ADC has an input coupled to receive the summed output analog signal from the analog input summing module and configured to provide a timing skew-calibrated digital output signal from the summed output analog signal. A digital output subtractor module is configured to provide a digital output signal at an output of the circuit from the digital output signal from the time-interleaved ADC and the digital sinusoidal signals from the multi-tone signal generator.
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