公开(公告)号：US09099486B2

公开(公告)日：2015-08-04

申请号：US13920874

申请日：2013-06-18

Applicant: NXP B.V.

Inventor： Matthias Merz ,  Casper Juffermans ,  Axel Nackaerts

IPC: G01N27/403 ,  H01L21/00 ,  H01L29/66 ,  G01N27/414

CPC classification number: H01L29/66 ,  G01N27/4145 ,  G01N27/4148 ,  H01L29/66007

Abstract: Disclosed is an integrated circuit comprising a substrate (10) carrying plurality of circuit elements (20); a metallization stack (30) over said substrate for providing interconnections to at least some of said circuit elements, the metallization stack comprising a plurality of patterned metal layers (31) spatially separated from each other by respective electrically insulating layers (32), at least some of said electrically insulating layers comprising conductive portions (33) that electrically interconnect portions of adjacent metal layers, wherein at least one of the patterned metallization layers comprises a plurality of ion-sensitive electrodes (34), each ion-sensitive electrode being electrically connected to at least one of said circuit elements, a plurality of sample volumes (50) extending into said metallization stack, each sample volume terminating at one of said ion-sensitive electrodes; and an ion-sensitive layer lining at least the ion-sensitive electrodes in said sample volumes. A method of manufacturing such an IC is also disclosed.

Abstract translation: 公开了一种集成电路，其包括承载多个电路元件（20）的基板（10）。 金属化堆叠（30），其位于所述衬底上方，用于提供至少一些所述电路元件的互连，所述金属化堆叠包括通过相应的电绝缘层（32）在空间上彼此分离的多个图案化金属层（31），至少 所述电绝缘层中的一些包括导电部分（33），导电部分相互连接相邻金属层的部分，其中图案化金属化层中的至少一个包括多个离子敏感电极（34），每个离子敏感电极电连接 至少一个所述电路元件，延伸到所述金属化堆叠中的多个样品体积（50），每个样品体积终止于所述离子敏感电极之一处; 以及至少衬在所述样品体积中的离子敏感电极的离子敏感层。 还公开了制造这种IC的方法。

公开(公告)号：US20130334619A1

公开(公告)日：2013-12-19

申请号：US13920874

申请日：2013-06-18

Applicant: NXP B.V.

Inventor： Matthias Merz ,  Casper Juffermans ,  Axel Nackaerts

IPC: H01L29/66

CPC classification number: H01L29/66 ,  G01N27/4145 ,  G01N27/4148 ,  H01L29/66007

Abstract: Disclosed is an integrated circuit comprising a substrate (10) carrying plurality of circuit elements (20); a metallization stack (30) over said substrate for providing interconnections to at least some of said circuit elements, the metallization stack comprising a plurality of patterned metal layers (31) spatially separated from each other by respective electrically insulating layers (32), at least some of said electrically insulating layers comprising conductive portions (33) that electrically interconnect portions of adjacent metal layers, wherein at least one of the patterned metallization layers comprises a plurality of ion-sensitive electrodes (34), each ion-sensitive electrode being electrically connected to at least one of said circuit elements, a plurality of sample volumes (50) extending into said metallization stack, each sample volume terminating at one of said ion-sensitive electrodes; and an ion-sensitive layer lining at least the ion-sensitive electrodes in said sample volumes. A method of manufacturing such an IC is also disclosed.

Abstract translation: 公开了一种集成电路，其包括承载多个电路元件（20）的基板（10）。 金属化堆叠（30），其位于所述衬底上方，用于提供至少一些所述电路元件的互连，所述金属化堆叠包括通过相应的电绝缘层（32）在空间上彼此分离的多个图案化金属层（31），至少 所述电绝缘层中的一些包括导电部分（33），导电部分相互连接相邻金属层的部分，其中图案化金属化层中的至少一个包括多个离子敏感电极（34），每个离子敏感电极电连接 至少一个所述电路元件，延伸到所述金属化堆叠中的多个样品体积（50），每个样品体积终止于所述离子敏感电极之一处; 以及至少衬在所述样品体积中的离子敏感电极的离子敏感层。 还公开了制造这种IC的方法。