-
公开(公告)号：US10447523B2
公开(公告)日：2019-10-15
申请号：US15619259
申请日：2017-06-09
Applicant: NXP B.V.
Inventor： Joerg Heinrich Walter Wenzel , Robert Rutten , Evert-Jan Pol , Jan van Sinderen , Tjeu van Ansem , Peter van de Haar
Abstract: The disclosure relates to an IQ mismatch correction module for a radio receiver, the IQ mismatch correction module comprising: an input terminal configured to receive an input signal; an output terminal configured to provide a filtered output signal; a mismatch detection module comprising: one or more bandpass filters configured to receive, from the input terminal or output terminal, a bandpass input signal and to pass a plurality of sub-bands of the bandpass input signal to provide respective bandpass filtered signals; one or more amplitude and phase mismatch detectors configured to determine amplitude and phase mismatch coefficients based on the bandpass filtered signals from the plurality of sub-bands; a transformation unit configured to apply a transformation to the amplitude and phase mismatch coefficients to provide correction filter coefficients for the plurality of sub-bands; and a filter module configured to: receive the filter coefficients for the plurality of sub-bands from the mismatch detection module; and filter the input signal in accordance with the received filter coefficients to provide the filtered output signal.
-
公开(公告)号：US20230305104A1
公开(公告)日：2023-09-28
申请号：US18182763
申请日：2023-03-13
Applicant: NXP B.V.
Inventor： Andries Pieter Hekstra , Alessio Filippi , Arie Geert Cornelis Koppelaar , Ryan Haoyun Wu , Dongyin Ren , Feike Guus Jansen , Jeroen Overdevest , Joerg Heinrich Walter Wenzel
CPC classification number: G01S7/354 , G01S13/584 , G01S7/356
Abstract: A radar receiver comprising: an ADC (510) that samples analogue intermediate frequency, IF, signalling in order to generate digital signalling, wherein the digital signalling comprises a plurality of digital-values; a digital processor that populates a 2-dimensional array of bin-values based on the digital-values, such that: a first axis of the 2-dimensional array is a fast time axis and a second axis of the 2-dimensional array is a slow time axis; and a sampling-rate-adjuster that is configured to set a sampling rate associated with the bin-values in the 2-dimensional array based on an index of the slow time axis. The digital processor also performs DFT calculations on the bin-values in the 2-dimensional array along the fast time axis and the slow time axis in order to determine the range and velocity of any detected objects.
-
公开(公告)号：US20180013604A1
公开(公告)日：2018-01-11
申请号：US15619259
申请日：2017-06-09
Applicant: NXP B.V.
Inventor： Joerg Heinrich Walter Wenzel , Robert Rutten , Evert-Jan Pol , Jan van Sinderen , Tjeu van Ansem , Peter van de Haar
CPC classification number: H04L27/364 , H04L1/20 , H04L27/3863
Abstract: The disclosure relates to an IQ mismatch correction module for a radio receiver, the IQ mismatch correction module comprising: an input terminal configured to receive an input signal; an output terminal configured to provide a filtered output signal; a mismatch detection module comprising: one or more bandpass filters configured to receive, from the input terminal or output terminal, a bandpass input signal and to pass a plurality of sub-bands of the bandpass input signal to provide respective bandpass filtered signals; one or more amplitude and phase mismatch detectors configured to determine amplitude and phase mismatch coefficients based on the bandpass filtered signals from the plurality of sub-bands; a transformation unit configured to apply a transformation to the amplitude and phase mismatch coefficients to provide correction filter coefficients for the plurality of sub-bands; and a filter module configured to: receive the filter coefficients for the plurality of sub-bands from the mismatch detection module; and filter the input signal in accordance with the received filter coefficients to provide the filtered output signal.
-
-
Search Results
3
records
(took 0.013 seconds)
