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公开(公告)号：US20230238974A1
公开(公告)日：2023-07-27
申请号：US18061601
申请日：2022-12-05
Applicant: NXP B.V.
Inventor： Robert Rutten , Muhammed Bolatkale , Lucien Johannes Breems
CPC classification number: H03M1/0621 , H03M1/1047 , H03M1/181
Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal. Hereby, the digital inputs provided to the DACs are non-randomized.
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公开(公告)号：US11522557B1
公开(公告)日：2022-12-06
申请号：US17388157
申请日：2021-07-29
Applicant: NXP B.V.
Inventor： Robert Rutten , Martin Kessel , Hendrik van der Ploeg , Lucien Johannes Breems , Muhammed Bolatkale , Evert-Jan Pol , Manfred Zupke , Bernard Burdiek , Johannes Hubertus Antonius Brekelmans , Shagun Bajoria
IPC: H03M3/00
Abstract: A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.
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公开(公告)号：US20170150521A1
公开(公告)日：2017-05-25
申请号：US15356451
申请日：2016-11-18
Applicant: NXP B.V.
Inventor： Jan Niehof , Shagun Bajoria , Muhammed Bolatkale , Robert Rutten , Lucien Johannes Breems , Johannes Hubertus Antonius Brekelmans
CPC classification number: H04W74/002 , H03M1/0678 , H03M1/08 , H03M1/123 , H03M1/183 , H04L5/0051
Abstract: A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analogue-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analogue-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.
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公开(公告)号：US20150200628A1
公开(公告)日：2015-07-16
申请号：US14588544
申请日：2015-01-02
Applicant: NXP B.V.
Inventor： Robert Rutten , Lucien Johannes Breems , Jan van Sinderen
CPC classification number: H03D7/1466 , H03D3/009 , H04B1/16 , H04B1/30 , H04B2001/305 , H04L27/3863
Abstract: An RF reception system and method uses IF quadrature mixing, in which there is further mixing and channel filtering in the digital domain, to isolate a frequency of interest. A coefficient estimator is used for generating a phase correction coefficient and an amplitude correction coefficient from filtered in-phase and quadrature desired signals and from filtered in-phase and quadrature image signals.
Abstract translation: RF接收系统和方法使用IF正交混合，其中在数字域中进一步进行混合和信道滤波，以隔离感兴趣的频率。 系数估计器用于从滤波的同相和正交期望信号以及滤波的同相和正交图像信号中产生相位校正系数和幅度校正系数。
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公开(公告)号：US10541699B1
公开(公告)日：2020-01-21
申请号：US16157355
申请日：2018-10-11
Applicant: NXP B.V.
Inventor： Robert Rutten , Massimo Ciacci , Manfred Zupke , Lucien Johannes Breems , Johannes Hubertus Antonius Brekelmans , Muhammed Bolatkale , Shagun Bajoria , Soheil Bahrami
Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal.
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Patent Agency Ranking
公开(公告)号：US09431962B2
公开(公告)日：2016-08-30
申请号：US14588544
申请日：2015-01-02
Applicant: NXP B.V.
Inventor： Robert Rutten , Lucien Johannes Breems , Jan van Sinderen
CPC classification number: H03D7/1466 , H03D3/009 , H04B1/16 , H04B1/30 , H04B2001/305 , H04L27/3863
Abstract: An RF reception system and method uses IF quadrature mixing, in which there is further mixing and channel filtering in the digital domain, to isolate a frequency of interest. A coefficient estimator is used for generating a phase correction coefficient and an amplitude correction coefficient from filtered in-phase and quadrature desired signals and from filtered in-phase and quadrature image signals.
Abstract translation: RF接收系统和方法使用IF正交混合，其中在数字域中进一步进行混合和信道滤波，以隔离感兴趣的频率。 系数估计器用于从滤波的同相和正交期望信号以及滤波的同相和正交图像信号中产生相位校正系数和幅度校正系数。
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公开(公告)号：US20240159888A1
公开(公告)日：2024-05-16
申请号：US18498138
申请日：2023-10-31
Applicant: NXP B.V.
Inventor： Robert Rutten , Andries Pieter Hekstra , Salvatore Drago , Tarik Saric
CPC classification number: G01S13/584 , G01S7/354 , G01S7/356 , G01S13/931
Abstract: A radar sensor comprising a chirp generator that is configured to provide radar signalling for transmission. The radar signalling comprises a sequence of radar chirps, and wherein each radar chirp has a chirp slope that defines the rate of change of frequency in the radar chirp. A mixer multiplies the transmitted radar signalling with a received, reflected version of the transmitted radar signalling in order to provide analogue intermediate frequency, IF, signalling. An ADC samples the IF signalling in order to generate digital signalling. A digital processor populates a 2-dimensional array of bin-values based on the digital-values, such that: a first axis of the 2-dimensional array is a fast time axis and a second axis of the 2-dimensional array is a slow time axis. A chirp slope frequency adjuster sets the chirp slope of the radar chirps based on an index in the sequence of radar chirps. The digital processor performs DFT calculations on the bin-values in the 2-dimensional array along the fast time axis and the slow time axis in order to determine the range and velocity of any detected objects.
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公开(公告)号：US10447523B2
公开(公告)日：2019-10-15
申请号：US15619259
申请日：2017-06-09
Applicant: NXP B.V.
Inventor： Joerg Heinrich Walter Wenzel , Robert Rutten , Evert-Jan Pol , Jan van Sinderen , Tjeu van Ansem , Peter van de Haar
Abstract: The disclosure relates to an IQ mismatch correction module for a radio receiver, the IQ mismatch correction module comprising: an input terminal configured to receive an input signal; an output terminal configured to provide a filtered output signal; a mismatch detection module comprising: one or more bandpass filters configured to receive, from the input terminal or output terminal, a bandpass input signal and to pass a plurality of sub-bands of the bandpass input signal to provide respective bandpass filtered signals; one or more amplitude and phase mismatch detectors configured to determine amplitude and phase mismatch coefficients based on the bandpass filtered signals from the plurality of sub-bands; a transformation unit configured to apply a transformation to the amplitude and phase mismatch coefficients to provide correction filter coefficients for the plurality of sub-bands; and a filter module configured to: receive the filter coefficients for the plurality of sub-bands from the mismatch detection module; and filter the input signal in accordance with the received filter coefficients to provide the filtered output signal.
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公开(公告)号：US20170149388A1
公开(公告)日：2017-05-25
申请号：US15342009
申请日：2016-11-02
Applicant: NXP B.V.
Inventor： Shagun Bajoria , Muhammed Bolatkale , Robert Rutten , Lucien Breems , Johannes Brekelmans , Jan Niehof
CPC classification number: H03D7/12 , H03F1/3211 , H03F3/45183 , H03F3/45475 , H03F2200/331 , H03F2203/45138 , H03M3/422 , H03M3/454 , H03M3/476
Abstract: A summing node is provided for summing a first and second differential signals. Each of the first and second differential signals comprise respective direct and inverse signal components. The summing node comprises a first differential transistor pair comprising a first and second input and coupled to a first and second output. The summing node further comprises a second differential transistor pair comprising a third and fourth input and coupled to the first and second output. The first and fourth inputs are respectively coupled to the direct and inverse signal components of the first differential signal and the second and third inputs are respectively coupled to the direct and inverse signal components of the second differential signal.
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10.发明授权公开(公告)号：US11502699B1
公开(公告)日：2022-11-15
申请号：US17357467
申请日：2021-06-24
Applicant: NXP B.V.
Inventor： Robert Rutten , Hendrik van der Ploeg , Lucien Johannes Breems , Martin Kessel , Muhammed Bolatkale , Bernard Burdiek , Manfred Zupke , Johannes Hubertus Antonius Brekelmans , Shagun Bajoria
IPC: H03M3/00
Abstract: A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.
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