公开(公告)号：US20210126638A1

公开(公告)日：2021-04-29

申请号：US17028150

申请日：2020-09-22

Applicant: NXP B.V.

Inventor： Klaas-Jan de Langen ,  Antonius Martinus Jacobus Daanen ,  Frederik van den Ende

IPC: H03K19/0185 ,  H03K19/003 ,  H03K3/356

Abstract: An apparatus comprising a first voltage domain circuit including a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based thereon with an increased voltage level of the high state, and provide said second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage, the at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, coupled to a CMOS inverter arrangement; the CMOS inverter arrangement of a first of the at least one stages configured to receive the first digital output signal and the CMOS inverter arrangement of a final stage of the at least one stages configured to output said second digital output signal.

公开(公告)号：US11520363B2

公开(公告)日：2022-12-06

申请号：US17028186

申请日：2020-09-22

Applicant: NXP B.V.

Inventor： Antonius Martinus Jacobus Daanen ,  Klaas-Jan de Langen ,  Sybren Matthias Bouwhuis

IPC: G05F1/56 ,  G05F1/46

Abstract: A system comprising: a LDO regulator configured to receive a supply voltage and provide an output voltage based on a function of the supply voltage, the LDO regulator switchable between at least a first and second mode, wherein the first and second modes each define the output voltage provided to the output terminal based on different functions of the supply voltage; and a digital logic controller configured to select the mode of the LDO regulator by control signalling to the LDO regulator, the digital logic controller configured to receive power for the provision of the control signalling from the LDO regulator; wherein the LDO regulator comprises LDO start-up circuitry configured to cause the LDO regulator, during start-up, to default to a predetermined one of the first and second mode and the LDO start-up circuitry further configured to prevent the digital logic controller from controlling the mode of the LDO regulator.

公开(公告)号：US11456745B2

公开(公告)日：2022-09-27

申请号：US17028150

申请日：2020-09-22

Applicant: NXP B.V.

Inventor： Klaas-Jan de Langen ,  Antonius Martinus Jacobus Daanen ,  Frederik van den Ende

IPC: H03K19/0185 ,  H03K3/356 ,  H03K19/003

Abstract: An apparatus comprising a first voltage domain circuit including a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based thereon with an increased voltage level of the high state, and provide said second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage, the at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, coupled to a CMOS inverter arrangement; the CMOS inverter arrangement of a first of the at least one stages configured to receive the first digital output signal and the CMOS inverter arrangement of a final stage of the at least one stages configured to output said second digital output signal.

公开(公告)号：US11424721B2

公开(公告)日：2022-08-23

申请号：US17069416

申请日：2020-10-13

Applicant: NXP B.V.

Inventor： Gian Hoogzaad ,  Guillaume Lebailly ,  Klaas-Jan de Langen

IPC: H03F1/22 ,  H03F3/195

Abstract: An RF amplifier for implementation in SiGe HBT technology is described. The RF amplifier has a cascode stage comprising a common base (CB) transistor and a common emitter (CE) transistor arranged in series between a first voltage rail and a second voltage rail. An RF input is coupled to the base of the CE transistor and an RF output is coupled to the collector of the CB transistor. The RF amplifier includes a CB power-down circuit arranged between the base of the CB transistor and the second voltage rail and a CE power-down circuit arranged between the base of the CE transistor and the second voltage rail. In a power-down mode the CE power-down circuit couples the base of the common-emitter-transistor to the second voltage rail. The CB power-down mode circuit couples the base of the CB transistor to the second voltage rail via a high-ohmic path.

公开(公告)号：US20210124381A1

公开(公告)日：2021-04-29

申请号：US17028186

申请日：2020-09-22

Applicant: NXP B.V.

Inventor： Antonius Martinus Jacobus Daanen ,  Klaas-Jan de Langen ,  Sybren Matthias Bouwhuis

IPC: G05F1/56 ,  G05F1/46

Abstract: A system comprising: a LDO regulator configured to receive a supply voltage and provide an output voltage based on a function of the supply voltage, the LDO regulator switchable between at least a first and second mode, wherein the first and second modes each define the output voltage provided to the output terminal based on different functions of the supply voltage; and a digital logic controller configured to select the mode of the LDO regulator by control signalling to the LDO regulator, the digital logic controller configured to receive power for the provision of the control signalling from the LDO regulator; wherein the LDO regulator comprises LDO start-up circuitry configured to cause the LDO regulator, during start-up, to default to a predetermined one of the first and second mode and the LDO start-up circuitry further configured to prevent the digital logic controller from controlling the mode of the LDO regulator.