-
公开(公告)号:US20250165739A1
公开(公告)日:2025-05-22
申请号:US18512188
申请日:2023-11-17
Applicant: NXP B.V.
IPC: G06K19/07
Abstract: A radio frequency (RF) voltage limiter for a radio frequency identification (RFID) transponder is provided. The RF voltage limiter includes an envelope detector configured to track an envelope of a signal received at the antenna. The envelope detector has an output for providing an envelope signal. A peak detector is included and has an input coupled to the output of the envelope detector. The peak detector includes a current mirror having an input coupled to the output of the envelope detector, and an output configured to provide a control signal. A shunt circuit is coupled to provide an impedance to the antenna in response to the control signal. The impedance decreases with an increasing voltage of the control signal to limit a maximum voltage at the antenna. In another embodiment, a method is provided for limiting a RF voltage at the antenna.
-
公开(公告)号:US20160006369A1
公开(公告)日:2016-01-07
申请号:US14791230
申请日:2015-07-02
Applicant: NXP B.V.
Inventor: Lukas Zoescher
CPC classification number: H02M7/537 , G06K19/0701 , H02M7/217 , H04B1/40
Abstract: A radio frequency transponder circuit, comprising: an AC-DC converter (70) connected to an RF input terminal (21a) and a DC output terminal (81) and operable to convert an RF signal (RFA) at the RF input terminal (21a) to a DC output signal (VDD) at the DC output terminal (81); and a voltage limiting circuit (50) connected to the RF input terminal (21a) and operable to limit the amplitude of the RF signal (RFA); wherein the voltage limiting circuit (50) comprises a NMOS limiting transistor (51) in parallel with a complimentary PMOS limiting transistor (52).
Abstract translation: 一种射频应答器电路,包括:连接到RF输入端子(21a)的AC-DC转换器(70)和DC输出端子(81),并且可操作以将RF输入端子(21a)处的RF信号(RFA) )到直流输出端子(81)处的直流输出信号(VDD); 以及连接到RF输入端子(21a)并且可操作地限制RF信号(RFA)的振幅的电压限制电路(50)。 其中所述电压限制电路(50)包括与互补PMOS限制晶体管(52)并联的NMOS限制晶体管(51)。
-
公开(公告)号:US10992504B2
公开(公告)日:2021-04-27
申请号:US16246297
申请日:2019-01-11
Applicant: NXP B.V.
Inventor: Lukas Zoescher , Erich Merlin , Ulrich Andreas Muehlmann
Abstract: In accordance with a first aspect of the present disclosure, an active load modulation (ALM) transceiver is provided, comprising a transmitter configured to send a transmit signal to an external device, wherein the transceiver is configured to adjust one or more parameters of the transmit signal at the end of at least one burst of said transmit signal. In accordance with a second aspect of the present disclosure, a method of operating an active load modulation (ALM) transceiver is conceived, comprising sending, by a transmitter of the transceiver, a transmit signal to an external device, and adjusting, by the transceiver, one or more parameters of the transmit signal at the end of at least one burst of said transmit signal.
-
公开(公告)号:US20190215203A1
公开(公告)日:2019-07-11
申请号:US16246297
申请日:2019-01-11
Applicant: NXP B.V.
Inventor: Lukas Zoescher , Erich Merlin , Ulrich Andreas Muehlmann
CPC classification number: H04L27/20 , H04B1/38 , H04B5/0031 , H04B5/0062 , H04L7/02
Abstract: In accordance with a first aspect of the present disclosure, an active load modulation (ALM) transceiver is provided, comprising a transmitter configured to send a transmit signal to an external device, wherein the transceiver is configured to adjust one or more parameters of the transmit signal at the end of at least one burst of said transmit signal. In accordance with a second aspect of the present disclosure, a method of operating an active load modulation (ALM) transceiver is conceived, comprising sending, by a transmitter of the transceiver, a transmit signal to an external device, and adjusting, by the transceiver, one or more parameters of the transmit signal at the end of at least one burst of said transmit signal.
-
公开(公告)号:US09716443B2
公开(公告)日:2017-07-25
申请号:US14791230
申请日:2015-07-02
Applicant: NXP B.V.
Inventor: Lukas Zoescher
CPC classification number: H02M7/537 , G06K19/0701 , H02M7/217 , H04B1/40
Abstract: A radio frequency transponder circuit, comprising: an AC-DC converter (70) connected to an RF input terminal (21a) and a DC output terminal (81) and operable to convert an RF signal (RFA) at the RF input terminal (21a) to a DC output signal (VDD) at the DC output terminal (81); and a voltage limiting circuit (50) connected to the RF input terminal (21a) and operable to limit the amplitude of the RF signal (RFA); wherein the voltage limiting circuit (50) comprises a NMOS limiting transistor (51) in parallel with a complimentary PMOS limiting transistor (52).
-
-
-
-