公开(公告)号：US11867571B2

公开(公告)日：2024-01-09

申请号：US17491744

申请日：2021-10-01

Applicant: NXP B.V.

Inventor： Ricardo Pureza Coimbra ,  Mateus Ribeiro Vanzella

IPC: G01K7/01 ,  G01K15/00 ,  H03K17/687

CPC classification number: G01K7/015 ,  G01K15/005 ,  H03K17/6872 ,  G01K7/01

Abstract: A low power temperature detection method, system, and apparatus sense when a temperature threshold is reached by connecting a current conveyor (111) with a startup bias circuit (112) having a first FET (P1) (connected to level shift a reference voltage to provide an input voltage VS1), a first diode-connected BJT (Q0) (connected to generate a base-emitter voltage based on the junction temperature), and a second FET (P2) (connected to level shift the base-emitter voltage), where the startup bias circuit (112) selectively connects the current conveyor (111) to ground to form a closed loop that is activated only when an emitter current at the first diode-connected BJT (Q0) enters a self-turned-on operation region, thereby activating the current conveyor to detect a temperature threshold being reached by the device junction temperature.

公开(公告)号：US11521693B2

公开(公告)日：2022-12-06

申请号：US17649443

申请日：2022-01-31

Applicant: NXP B.V.

Inventor： Ricardo Pureza Coimbra ,  Mateus Ribeiro Vanzella ,  Luis Enrique Del Castillo

IPC: G11C27/02

Abstract: A sample and hold circuit configured to sample a current includes an input node to receive the current, a capacitor coupled with a sampling node and a reference voltage node, switch between the input node and the sampling node, a controlled current source coupled to the input node, a current mirror circuit having connections each providing a mirrored current, wherein at least one of said connections provides an output node, and a transistor arrangement. The transistor arrangement includes a control MOSFET in series with a series connected chain of cascaded cells. The control MOSFET and each of said cascaded cells are coupled to the current mirror circuit and each of the cascaded cells includes a pair of MOSFETs arranged to provide a voltage difference including a difference between a gate-source voltage of a first of the pair and a gate-source voltage of a second of the pair.

公开(公告)号：US20220254424A1

公开(公告)日：2022-08-11

申请号：US17649443

申请日：2022-01-31

Applicant: NXP B.V.

Inventor： Ricardo Pureza Coimbra ,  Mateus Ribeiro Vanzella ,  Luis Enrique Del Castillo

IPC: G11C27/02

Abstract: A sample and hold circuit configured to sample a current includes an input node to receive the current, a capacitor coupled with a sampling node and a reference voltage node, switch between the input node and the sampling node, a controlled current source coupled to the input node, a current mirror circuit having connections each providing a mirrored current, wherein at least one of said connections provides an output node, and a transistor arrangement. The transistor arrangement includes a control MOSFET in series with a series connected chain of cascaded cells. The control MOSFET and each of said cascaded cells are coupled to the current mirror circuit and each of the cascaded cells includes a pair of MOSFETs arranged to provide a voltage difference including a difference between a gate-source voltage of a first of the pair and a gate-source voltage of a second of the pair.