公开(公告)号：US20230071036A1

公开(公告)日：2023-03-09

申请号：US17468191

申请日：2021-09-07

Applicant: NXP B.V.

Inventor： Ricardo Pureza Coimbra ,  Luis Enrique Del Castillo

IPC: H03B5/20 ,  H03K5/24 ,  H03K3/037

Abstract: A low power relaxation oscillator circuit includes, in one embodiment, a first comparator for comparing voltages at first and second inputs, respectively, a first capacitor coupled to the first input of the first comparator, and a first circuit configured for charging the first capacitor to a first voltage. The first voltage is related to a propagation delay of the first comparator.

公开(公告)号：US11689157B2

公开(公告)日：2023-06-27

申请号：US17468191

申请日：2021-09-07

Applicant: NXP B.V.

Inventor： Ricardo Pureza Coimbra ,  Luis Enrique Del Castillo

IPC: H03B5/20 ,  H03K3/037 ,  H03K5/24

CPC classification number: H03B5/20 ,  H03K3/037 ,  H03K5/24

Abstract: A low power relaxation oscillator circuit includes, in one embodiment, a first comparator for comparing voltages at first and second inputs, respectively, a first capacitor coupled to the first input of the first comparator, and a first circuit configured for charging the first capacitor to a first voltage. The first voltage is related to a propagation delay of the first comparator.

公开(公告)号：US11521693B2

公开(公告)日：2022-12-06

申请号：US17649443

申请日：2022-01-31

Applicant: NXP B.V.

Inventor： Ricardo Pureza Coimbra ,  Mateus Ribeiro Vanzella ,  Luis Enrique Del Castillo

IPC: G11C27/02

Abstract: A sample and hold circuit configured to sample a current includes an input node to receive the current, a capacitor coupled with a sampling node and a reference voltage node, switch between the input node and the sampling node, a controlled current source coupled to the input node, a current mirror circuit having connections each providing a mirrored current, wherein at least one of said connections provides an output node, and a transistor arrangement. The transistor arrangement includes a control MOSFET in series with a series connected chain of cascaded cells. The control MOSFET and each of said cascaded cells are coupled to the current mirror circuit and each of the cascaded cells includes a pair of MOSFETs arranged to provide a voltage difference including a difference between a gate-source voltage of a first of the pair and a gate-source voltage of a second of the pair.

公开(公告)号：US20220254424A1

公开(公告)日：2022-08-11

申请号：US17649443

申请日：2022-01-31

Applicant: NXP B.V.

Inventor： Ricardo Pureza Coimbra ,  Mateus Ribeiro Vanzella ,  Luis Enrique Del Castillo

IPC: G11C27/02

Abstract: A sample and hold circuit configured to sample a current includes an input node to receive the current, a capacitor coupled with a sampling node and a reference voltage node, switch between the input node and the sampling node, a controlled current source coupled to the input node, a current mirror circuit having connections each providing a mirrored current, wherein at least one of said connections provides an output node, and a transistor arrangement. The transistor arrangement includes a control MOSFET in series with a series connected chain of cascaded cells. The control MOSFET and each of said cascaded cells are coupled to the current mirror circuit and each of the cascaded cells includes a pair of MOSFETs arranged to provide a voltage difference including a difference between a gate-source voltage of a first of the pair and a gate-source voltage of a second of the pair.