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公开(公告)号：US11251780B1
公开(公告)日：2022-02-15
申请号：US17302048
申请日：2021-04-22
Applicant: NXP B.V.
Inventor： Ricardo Pureza Coimbra , Vitor Moreira Gomes
IPC: H03K19/0185 , H03K3/037
Abstract: An integrated circuit device includes a level shifter circuit with a supply voltage rail to provide a supply voltage, a first pull-up circuit coupled between the supply voltage rail and a first node, a second pull-up circuit coupled between the supply voltage rail and a second node, a first switch including a first terminal coupled to the supply voltage rail, a second terminal coupled to the first node, and a control terminal coupled to the second node, and an inverter including an input terminal coupled to the first node, a voltage supply terminal coupled to the supply voltage, and an output terminal to provide an output voltage from the level shifter circuit.
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公开(公告)号：US20230176097A1
公开(公告)日：2023-06-08
申请号：US17643052
申请日：2021-12-07
Applicant: NXP B.V.
IPC: G01R19/257 , H03M1/12
CPC classification number: G01R19/257 , H03M1/1245
Abstract: An integrated circuit includes an analog-to-digital converter (ADC) configured to receive input voltage, and first and second reference voltages, and outputs digital code representing ratios between the input voltage and the first and the second reference voltages. The first and second reference voltages are generated by a reference generator using different current densities. During a first stage, the ADC samples the first input voltage and the first reference voltage and transfers equivalent charge of the sampled first input voltage and first reference voltage to an integration capacitor. During a second stage, the ADC samples the second reference voltage and transfers equivalent charge of the sampled second reference voltage to the integration capacitor. The ADC provides one bit of digital code based on total charge stored on the integration capacitor after the transfers of charge of the sampled input voltage, and the sampled first and second reference voltages.
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公开(公告)号：US20230071036A1
公开(公告)日：2023-03-09
申请号：US17468191
申请日：2021-09-07
Applicant: NXP B.V.
Inventor： Ricardo Pureza Coimbra , Luis Enrique Del Castillo
Abstract: A low power relaxation oscillator circuit includes, in one embodiment, a first comparator for comparing voltages at first and second inputs, respectively, a first capacitor coupled to the first input of the first comparator, and a first circuit configured for charging the first capacitor to a first voltage. The first voltage is related to a propagation delay of the first comparator.
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公开(公告)号：US11368126B1
公开(公告)日：2022-06-21
申请号：US17444320
申请日：2021-08-03
Applicant: NXP B.V.
Abstract: A first switch is operable to couple a start-up oscillator circuit to a first crystal pin during operation in a start-up mode and decouple the start-up oscillator circuit from the first crystal pin during operation in a normal mode, and a second switch is operable to couple the start-up oscillator circuit to a second crystal pin during operation in the start-up mode and decouple the start-up oscillator circuit from the second crystal pin during operation in the normal mode. A switched oscillator circuit is coupled to the startup oscillator during operation in the startup mode, and to the first and second crystal pins during operation in the start-up and normal modes. The switched oscillator circuit includes a sample and charge circuit which is configured to sample a direct current (DC) level of the first crystal pin and pre-charge a first coupling capacitor during operation in the startup mode.
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公开(公告)号：US11353910B1
公开(公告)日：2022-06-07
申请号：US17302399
申请日：2021-04-30
Applicant: NXP B.V.
Inventor： Sanjay Kumar Wadhwa , Ricardo Pureza Coimbra , Jaideep Banerjee
IPC: G05F3/26
Abstract: A bandgap voltage regulator includes a proportional-to-absolute-temperature (PTAT) circuit, an amplifier, and a driver circuit. The PTAT circuit can include various transistors that output a corresponding control voltage. The amplifier generates another control voltage to compensate base-current variations associated with the transistors of the PTAT circuit. The control voltage is generated by the amplifier based on the control voltage outputted by the PTAT circuit, and one of a base-emitter voltage associated with a transistor of the PTAT circuit, a scaled down version of the control voltage outputted by the amplifier, and a scaled down version of the base-emitter voltage. The driver circuit outputs, based on a supply voltage and the control voltages outputted by the PTAT circuit, a reference voltage for driving a functional circuit.
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Patent Agency Ranking
公开(公告)号：US11867571B2
公开(公告)日：2024-01-09
申请号：US17491744
申请日：2021-10-01
Applicant: NXP B.V.
Inventor： Ricardo Pureza Coimbra , Mateus Ribeiro Vanzella
IPC: G01K7/01 , G01K15/00 , H03K17/687
CPC classification number: G01K7/015 , G01K15/005 , H03K17/6872 , G01K7/01
Abstract: A low power temperature detection method, system, and apparatus sense when a temperature threshold is reached by connecting a current conveyor (111) with a startup bias circuit (112) having a first FET (P1) (connected to level shift a reference voltage to provide an input voltage VS1), a first diode-connected BJT (Q0) (connected to generate a base-emitter voltage based on the junction temperature), and a second FET (P2) (connected to level shift the base-emitter voltage), where the startup bias circuit (112) selectively connects the current conveyor (111) to ground to form a closed loop that is activated only when an emitter current at the first diode-connected BJT (Q0) enters a self-turned-on operation region, thereby activating the current conveyor to detect a temperature threshold being reached by the device junction temperature.
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公开(公告)号：US11689157B2
公开(公告)日：2023-06-27
申请号：US17468191
申请日：2021-09-07
Applicant: NXP B.V.
Inventor： Ricardo Pureza Coimbra , Luis Enrique Del Castillo
Abstract: A low power relaxation oscillator circuit includes, in one embodiment, a first comparator for comparing voltages at first and second inputs, respectively, a first capacitor coupled to the first input of the first comparator, and a first circuit configured for charging the first capacitor to a first voltage. The first voltage is related to a propagation delay of the first comparator.
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公开(公告)号：US11733277B2
公开(公告)日：2023-08-22
申请号：US17643052
申请日：2021-12-07
Applicant: NXP B.V.
IPC: H03M1/12 , G01R19/257
CPC classification number: G01R19/257 , H03M1/1245
Abstract: An integrated circuit includes an analog-to-digital converter (ADC) configured to receive input voltage, and first and second reference voltages, and outputs digital code representing ratios between the input voltage and the first and the second reference voltages. The first and second reference voltages are generated by a reference generator using different current densities. During a first stage, the ADC samples the first input voltage and the first reference voltage and transfers equivalent charge of the sampled first input voltage and first reference voltage to an integration capacitor. During a second stage, the ADC samples the second reference voltage and transfers equivalent charge of the sampled second reference voltage to the integration capacitor. The ADC provides one bit of digital code based on total charge stored on the integration capacitor after the transfers of charge of the sampled input voltage, and the sampled first and second reference voltages.
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公开(公告)号：US11521693B2
公开(公告)日：2022-12-06
申请号：US17649443
申请日：2022-01-31
Applicant: NXP B.V.
IPC: G11C27/02
Abstract: A sample and hold circuit configured to sample a current includes an input node to receive the current, a capacitor coupled with a sampling node and a reference voltage node, switch between the input node and the sampling node, a controlled current source coupled to the input node, a current mirror circuit having connections each providing a mirrored current, wherein at least one of said connections provides an output node, and a transistor arrangement. The transistor arrangement includes a control MOSFET in series with a series connected chain of cascaded cells. The control MOSFET and each of said cascaded cells are coupled to the current mirror circuit and each of the cascaded cells includes a pair of MOSFETs arranged to provide a voltage difference including a difference between a gate-source voltage of a first of the pair and a gate-source voltage of a second of the pair.
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公开(公告)号：US20220254424A1
公开(公告)日：2022-08-11
申请号：US17649443
申请日：2022-01-31
Applicant: NXP B.V.
IPC: G11C27/02
Abstract: A sample and hold circuit configured to sample a current includes an input node to receive the current, a capacitor coupled with a sampling node and a reference voltage node, switch between the input node and the sampling node, a controlled current source coupled to the input node, a current mirror circuit having connections each providing a mirrored current, wherein at least one of said connections provides an output node, and a transistor arrangement. The transistor arrangement includes a control MOSFET in series with a series connected chain of cascaded cells. The control MOSFET and each of said cascaded cells are coupled to the current mirror circuit and each of the cascaded cells includes a pair of MOSFETs arranged to provide a voltage difference including a difference between a gate-source voltage of a first of the pair and a gate-source voltage of a second of the pair.
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