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公开(公告)号：US20250055466A1
公开(公告)日：2025-02-13
申请号：US18798617
申请日：2024-08-08
Applicant: NXP B.V.
Inventor： Mathieu Périn , Stefano Dal Toso , Khurram Waheed
Abstract: Provided is a phase-lock loop gear shifter that includes: an input for receiving a loop gain that is dynamically controllable; an input for receiving a phase-error signal; a subtractor configured to provide a gain difference between the loop gain input at a second time and the loop gain input at a first time, the first time being earlier than the second time; a module that determines a characteristic phase-error value based on the phase-error signal; and a multiplier that multiplies the gain difference by the characteristic phase-error value to provide a control-signal correction value.
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公开(公告)号：US20250062770A1
公开(公告)日：2025-02-20
申请号：US18799117
申请日：2024-08-09
Applicant: NXP B.V.
Inventor： Mathieu Périn , Stefano Dal Toso , Khurram Waheed
Abstract: Provided is a phase-lock loop that includes: an oscillator having an input for receiving a control signal and an output for providing an output signal having a frequency based on the control signal; a phase detector having a first input for receiving a reference signal, a second input coupled to the output of the oscillator for receiving a feedback signal, and an output for providing a phase-error signal that is indicative of a phase difference between the reference signal and the feedback signal; and a loop filter having a first input coupled to the output of the phase detector, a second input for receiving a proportional-phase-compensation value, and an output for providing the control signal to the oscillator. The control signal comprises a proportional component which is a combination of the phase-error signal and the proportional-phase-compensation value.
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公开(公告)号：US11489532B2
公开(公告)日：2022-11-01
申请号：US17241578
申请日：2021-04-27
Applicant: NXP B.V.
Inventor： Mathieu Périn , Stefano Dal Toso
Abstract: An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.
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公开(公告)号：US20220263512A1
公开(公告)日：2022-08-18
申请号：US17241578
申请日：2021-04-27
Applicant: NXP B.V.
Inventor： Mathieu Périn , Stefano Dal Toso
Abstract: An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.
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