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公开(公告)号：US12231136B2
公开(公告)日：2025-02-18
申请号：US17655399
申请日：2022-03-18
Applicant: NXP B.V.
Inventor： Mathieu Perin , Stefano Dal Toso , Khurram Waheed , Claudio Gustavo Rey
Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. A first frequency and first relative phase of a first output signal are locked to a frequency and a phase of a first input signal. A second frequency and second relative phase of a second output signal are locked to a frequency and a phase of a second input signal. A correction to the PLL is applied to perform one of: adjusting the second relative phase to equal the first relative phase and adjusting the oscillator frequency.
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公开(公告)号：US11979157B2
公开(公告)日：2024-05-07
申请号：US18061674
申请日：2022-12-05
Applicant: NXP B.V.
Inventor： Stefano Dal Toso , Olivier Susplugas
CPC classification number: H03K3/35613 , G06F1/06 , G06F1/08 , H03K5/2481
Abstract: It is described a signal converter device (100) for converting a single-ended signal to a differential signal, the device (100) comprising:
i) a multiplier device (110), configured to
receive a single-ended incoming signal (105), and
multiply the incoming signal (105) to provide a multiplied signal (115); and
ii) a divider device (120), configured to
receive the multiplied signal (115), and
divide the multiplied signal (115) to provide a differential signal (125a, 125b).
Further, a corresponding signal conversion method is described.-
公开(公告)号：US20230246635A1
公开(公告)日：2023-08-03
申请号：US18061674
申请日：2022-12-05
Applicant: NXP B.V.
Inventor： Stefano Dal Toso , Olivier Susplugas
CPC classification number: H03K3/35613 , H03K5/2481
Abstract: It is described a signal converter device (100) for converting a single-ended signal to a differential signal, the device (100) comprising:
i) a multiplier device (110), configured to
receive a single-ended incoming signal (105), and
multiply the incoming signal (105) to provide a multiplied signal (115); and
ii) a divider device (120), configured to
receive the multiplied signal (115), and
divide the multiplied signal (115) to provide a differential signal (125a, 125b).
Further, a corresponding signal conversion method is described.-
公开(公告)号：US11545982B2
公开(公告)日：2023-01-03
申请号：US17656124
申请日：2022-03-23
Applicant: NXP B.V.
Inventor： Mathieu Perin , Stefano Dal Toso , Khurram Waheed , Claudio Gustavo Rey
Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (ΔΦLO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.
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公开(公告)号：US20220321132A1
公开(公告)日：2022-10-06
申请号：US17656124
申请日：2022-03-23
Applicant: NXP B.V.
Inventor： Mathieu Perin , Stefano Dal Toso , Khurram Waheed , Claudio Gustavo Rey
Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (ΔΦLO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.
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Patent Agency Ranking
公开(公告)号：US20220311446A1
公开(公告)日：2022-09-29
申请号：US17655399
申请日：2022-03-18
Applicant: NXP B.V.
Inventor： Mathieu Perin , Stefano Dal Toso , Khurram Waheed , Claudio Gustavo Rey
Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. A first frequency and first relative phase of a first output signal are locked to a frequency and a phase of a first input signal. A second frequency and second relative phase of a second output signal are locked to a frequency and a phase of a second input signal. A correction to the PLL is applied to perform one of: adjusting the second relative phase to equal the first relative phase and adjusting the oscillator frequency.
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公开(公告)号：US20210126584A1
公开(公告)日：2021-04-29
申请号：US17061887
申请日：2020-10-02
Applicant: NXP B.V.
Inventor： Mathieu Perin , Stefano Dal Toso
IPC: H03B5/12
Abstract: A variable reactance apparatus, tunable oscillator and method for changing a gain associated with an input signal of a tunable oscillator are disclosed. An embodiment of the variable reactance apparatus comprises includes a plurality of unit variable reactance structures comprising including respective control input nodes, and a control circuit configured to connect each of the control input nodes to a respective signal from among a plurality of signals comprising including a first tuning signal and a second tuning signal. An embodiment of a tunable oscillator comprises includes a resonance circuit, a negative impedance structure and a variable reactance apparatus configured for tuning of the oscillator. An embodiment of a method comprises includes altering connections of first and second tuning signals to control input nodes of respective first and second sets of unit variable reactance structures while holding constant a sum of the number of unit variable reactance structures in the first and second sets.
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公开(公告)号：US20250055466A1
公开(公告)日：2025-02-13
申请号：US18798617
申请日：2024-08-08
Applicant: NXP B.V.
Inventor： Mathieu Périn , Stefano Dal Toso , Khurram Waheed
Abstract: Provided is a phase-lock loop gear shifter that includes: an input for receiving a loop gain that is dynamically controllable; an input for receiving a phase-error signal; a subtractor configured to provide a gain difference between the loop gain input at a second time and the loop gain input at a first time, the first time being earlier than the second time; a module that determines a characteristic phase-error value based on the phase-error signal; and a multiplier that multiplies the gain difference by the characteristic phase-error value to provide a control-signal correction value.
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公开(公告)号：US11114978B2
公开(公告)日：2021-09-07
申请号：US17061887
申请日：2020-10-02
Applicant: NXP B.V.
Inventor： Mathieu Perin , Stefano Dal Toso
Abstract: A variable reactance apparatus, tunable oscillator and method for changing a gain associated with an input signal of a tunable oscillator are disclosed. An embodiment of the variable reactance apparatus includes a plurality of unit variable reactance structures including respective control input nodes, and a control circuit configured to connect each of the control input nodes to a respective signal from among a plurality of signals including a first tuning signal and a second tuning signal. An embodiment of a tunable oscillator includes a resonance circuit, a negative impedance structure and a variable reactance apparatus configured for tuning of the oscillator. An embodiment of a method includes altering connections of first and second tuning signals to control input nodes of respective first and second sets of unit variable reactance structures while holding constant a sum of the number of unit variable reactance structures in the first and second sets.
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公开(公告)号：US20250062770A1
公开(公告)日：2025-02-20
申请号：US18799117
申请日：2024-08-09
Applicant: NXP B.V.
Inventor： Mathieu Périn , Stefano Dal Toso , Khurram Waheed
Abstract: Provided is a phase-lock loop that includes: an oscillator having an input for receiving a control signal and an output for providing an output signal having a frequency based on the control signal; a phase detector having a first input for receiving a reference signal, a second input coupled to the output of the oscillator for receiving a feedback signal, and an output for providing a phase-error signal that is indicative of a phase difference between the reference signal and the feedback signal; and a loop filter having a first input coupled to the output of the phase detector, a second input for receiving a proportional-phase-compensation value, and an output for providing the control signal to the oscillator. The control signal comprises a proportional component which is a combination of the phase-error signal and the proportional-phase-compensation value.
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