公开(公告)号：US20240234222A9

公开(公告)日：2024-07-11

申请号：US18048972

申请日：2022-10-24

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Zhiwei Gong ,  Neil Thomas Tracht

IPC: H01L23/04 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/041 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227

Abstract: A method of forming a semiconductor device is provided. The method includes forming a first cavity at a first major surface of a first encapsulant. A first semiconductor die is affixed on the first major surface of the first encapsulant and a second semiconductor die is affixed on a bottom surface of the first cavity. A second encapsulant encapsulates the first semiconductor die, the second semiconductor die, and at least exposed portions of the first major surface of the first encapsulant. A package substrate is formed on a first major surface of the second encapsulant. The package substrate includes conductive traces interconnected to the first semiconductor die and the second semiconductor die.

公开(公告)号：US20240136238A1

公开(公告)日：2024-04-25

申请号：US18048972

申请日：2022-10-23

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Zhiwei Gong ,  Neil Thomas Tracht

IPC: H01L23/04 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/041 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227

Abstract: A method of forming a semiconductor device is provided. The method includes forming a first cavity at a first major surface of a first encapsulant. A first semiconductor die is affixed on the first major surface of the first encapsulant and a second semiconductor die is affixed on a bottom surface of the first cavity. A second encapsulant encapsulates the first semiconductor die, the second semiconductor die, and at least exposed portions of the first major surface of the first encapsulant. A package substrate is formed on a first major surface of the second encapsulant. The package substrate includes conductive traces interconnected to the first semiconductor die and the second semiconductor die.