公开(公告)号：US11935753B2

公开(公告)日：2024-03-19

申请号：US17546449

申请日：2021-12-09

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L21/283 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/283 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/05558 ,  H01L2924/3511

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

公开(公告)号：US20230378107A1

公开(公告)日：2023-11-23

申请号：US17664117

申请日：2022-05-19

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Yufu Liu ,  Tsung Nan Lo ,  Wen Hung Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L21/56 ,  H01L24/03 ,  H01L2224/0233 ,  H01L2224/0401 ,  H01L2224/02311

Abstract: A semiconductor device package includes a semiconductor device and an electrically conductive pad disposed in contact with a surface of the semiconductor device. The semiconductor device package further includes a redistribution layer (RDL) formed over the electrically conductive pad and the surface of the semiconductor device, and an electrical connector disposed over and electrically coupled to the RDL. The RDL includes a first passivation layer disposed over a surface of the semiconductor device and the electrically conductive pad, and further includes an RDL trace. The RDL trace includes a first portion in contact with the electrically conductive pad, a second portion in contact with one of the electrical connector or an underlying metallization layer in contact with the electrical connector, and a third portion having a non-planar and undulating configuration relative to the surface of the semiconductor device.

公开(公告)号：US20240387271A1

公开(公告)日：2024-11-21

申请号：US18787368

申请日：2024-07-29

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Yufu Liu

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: Packaged semiconductor devices are disclosed, comprising: a semiconductor die having a top major surface with a plurality of contact pads thereon, and four sides, wherein the sides are stepped such that a lower portion of each side extends laterally beyond a respective upper portion; encapsulating material encapsulating the top major surface and the upper portion of each of the sides wherein the semiconductor die is exposed at the lower portion of each of the sides; a contact-redistribution structure on the encapsulating material over the top major surface of the semiconductor die; a plurality of metallic studs extending through the encapsulating material, and providing electrical contact between the contact pads and the contact-redistribution structure. Corresponding methods are also disclosed.

公开(公告)号：US20240194486A1

公开(公告)日：2024-06-13

申请号：US18444826

申请日：2024-02-19

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L21/283 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/283 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/05558 ,  H01L2924/3511

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

公开(公告)号：US20240105659A1

公开(公告)日：2024-03-28

申请号：US17936042

申请日：2022-09-28

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Yufu Liu ,  Wen Hung Huang ,  Tsung Nan Lo

IPC: H01L23/00

CPC classification number: H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/13 ,  H01L2224/13006 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/73101

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over a semiconductor die. A portion of the RDL contacts a die pad of the semiconductor die. A metal layer is formed on a top surface and sidewalls of the RDL and configured to encase the RDL. A non-conductive layer is formed over the metal layer and underlying RDL. An opening in the non-conductive layer is formed exposing a portion of the metal layer formed on the RDL. An under-bump metallization (UBM) is formed in the opening and conductively connected to the die pad by way of the metal layer and RDL.

公开(公告)号：US20230014470A1

公开(公告)日：2023-01-19

申请号：US17377507

申请日：2021-07-16

Applicant: NXP B.V

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Yufu Liu

IPC: H01L21/78 ,  H01L23/31 ,  H01L21/56

Abstract: Packaged semiconductor devices are disclosed, comprising: a semiconductor die having a top major surface with a plurality of contact pads thereon, and four sides, wherein the sides are stepped such that a lower portion of each side extends laterally beyond a respective upper portion; encapsulating material encapsulating the top major surface and the upper portion of each of the sides wherein the semiconductor die is exposed at the lower portion of each of the sides; a contact-redistribution structure on the encapsulating material over the top major surface of the semiconductor die; a plurality of metallic studs extending through the encapsulating material, and providing electrical contact between the contact pads and the contact-redistribution structure. Corresponding methods are also disclosed.

公开(公告)号：US20240234222A9

公开(公告)日：2024-07-11

申请号：US18048972

申请日：2022-10-24

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Zhiwei Gong ,  Neil Thomas Tracht

IPC: H01L23/04 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/041 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227

Abstract: A method of forming a semiconductor device is provided. The method includes forming a first cavity at a first major surface of a first encapsulant. A first semiconductor die is affixed on the first major surface of the first encapsulant and a second semiconductor die is affixed on a bottom surface of the first cavity. A second encapsulant encapsulates the first semiconductor die, the second semiconductor die, and at least exposed portions of the first major surface of the first encapsulant. A package substrate is formed on a first major surface of the second encapsulant. The package substrate includes conductive traces interconnected to the first semiconductor die and the second semiconductor die.

公开(公告)号：US20240136238A1

公开(公告)日：2024-04-25

申请号：US18048972

申请日：2022-10-23

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Zhiwei Gong ,  Neil Thomas Tracht

IPC: H01L23/04 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/041 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227

Abstract: A method of forming a semiconductor device is provided. The method includes forming a first cavity at a first major surface of a first encapsulant. A first semiconductor die is affixed on the first major surface of the first encapsulant and a second semiconductor die is affixed on a bottom surface of the first cavity. A second encapsulant encapsulates the first semiconductor die, the second semiconductor die, and at least exposed portions of the first major surface of the first encapsulant. A package substrate is formed on a first major surface of the second encapsulant. The package substrate includes conductive traces interconnected to the first semiconductor die and the second semiconductor die.

公开(公告)号：US20230187299A1

公开(公告)日：2023-06-15

申请号：US17546398

申请日：2021-12-09

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Che Ming Fang ,  Yufu Liu ,  Wen Hung Huang

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1191 ,  H01L2224/05024 ,  H01L2224/13022

Abstract: A method for manufacturing a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices. Each integrated circuit device extends into the semiconductor wafer to a first depth. Prior to singulation of the integrated circuit devices on the semiconductor wafer, the method further includes forming a cut between the integrated circuit devices. The cut extends to at least the first depth, but does not extend completely through the semiconductor wafer. The cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on each integrated circuit device, a passivation layer on a top surface and on the edges.

公开(公告)号：US20220384372A1

公开(公告)日：2022-12-01

申请号：US17333837

申请日：2021-05-28

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L23/00 ,  C09D5/24 ,  C09D179/04 ,  C09D179/08

Abstract: A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.