公开(公告)号：US20240347508A1

公开(公告)日：2024-10-17

申请号：US18584007

申请日：2024-02-22

申请人： Samsung Electronics Co., Ltd.

发明人： Jihyun Lim

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/04 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

CPC分类号： H01L25/0655 ,  H01L23/041 ,  H01L23/3107 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06568

摘要： A semiconductor package includes a lower redistribution wiring layer having lower redistribution wirings; an encapsulation structure on the lower redistribution wiring layer; a plurality of conductive bumps between the lower redistribution wiring layer and the encapsulation structure; and an adhesive layer attaching the lower redistribution wiring layer and the encapsulation structure. The encapsulation structure includes a core substrate having a cavity formed therein, at least one semiconductor chip in the cavity such that a front surface on which chip pads are formed faces the lower redistribution wiring layer, and an upper redistribution wiring layer covering an upper surface of the core substrate and having upper redistribution wiring layers that are electrically connected to conductive structures of the core substrate.

公开(公告)号：US11916001B2

公开(公告)日：2024-02-27

申请号：US16961774

申请日：2018-12-13

申请人： Mitsubishi Electric Corporation

发明人： Kozo Harada

IPC分类号： H01L23/498 ,  H01L23/04 ,  H01L23/14 ,  H01L23/31 ,  H02M7/5387 ,  H02P27/08

CPC分类号： H01L23/49811 ,  H01L23/041 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3135 ,  H02M7/53871 ,  H02P27/08

摘要： A semiconductor power module includes a base plate, an insulating substrate, a power semiconductor element, an external terminal, a main terminal, a connected body, a case, a highly-insulating voltage-resisting resin material, a sealing resin, and a cover. The main terminal is connected to the connected body. The connected body is directly joined to the metal plate. The connected body is provided with a receiving section in which the main terminal is received. The receiving section is provided with a slit portion. The slit portion extends from a lower end side of the receiving section toward an upper end side thereof. The lower end side is located on a side close to the insulating substrate. The upper end side is located opposite to the side close to the insulating substrate.

公开(公告)号：US20240063066A1

公开(公告)日：2024-02-22

申请号：US17891665

申请日：2022-08-19

申请人： Intel Corporation

发明人： Omkar G. Karhade ,  Tomita Yoshihiro ,  Adel A. Elsherbini ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Haris Khan Niazi ,  Yi Shi ,  Batao Zhang ,  Wenhao Li ,  Feras Eid

IPC分类号： H01L23/04 ,  H01L25/065 ,  H01L23/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/46 ,  H01L23/367

CPC分类号： H01L23/041 ,  H01L25/0652 ,  H01L23/18 ,  H01L24/08 ,  H01L23/481 ,  H01L23/46 ,  H01L23/367 ,  H01L2224/08145 ,  H01L2224/05599 ,  H01L24/05 ,  H01L2224/80379 ,  H01L24/80 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2224/131 ,  H01L24/13 ,  H01L2224/29099 ,  H01L24/29

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.

公开(公告)号：US20230395485A1

公开(公告)日：2023-12-07

申请号：US18454413

申请日：2023-08-23

申请人： Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

发明人： Tomohiro IGUCHI ,  Tatsuya HIRAKAWA

IPC分类号： H01L23/498 ,  H01L23/04 ,  H01L23/31

CPC分类号： H01L23/49861 ,  H01L23/041 ,  H01L23/3121 ,  H01L23/49811

摘要： A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer on a surface of the insulating substrate; a semiconductor chip including an upper electrode and a lower electrode, the upper electrode being electrically connected to the first metal layer, the lower electrode being electrically connected to the second metal layer; a first main terminal including a first end and a second end, the first end being electrically connected to the first metal layer; a second main terminal including a third end and a fourth end, the third end being electrically connected to the second metal layer; a first detection terminal being electrically connected between the first end and the second end of the first main terminal; and a second detection terminal being electrically connected to the first metal layer.

公开(公告)号：US20180315721A1

公开(公告)日：2018-11-01

申请号：US15945778

申请日：2018-04-05

申请人： FUJITSU LIMITED

发明人： Masaru Sato ,  Yukiyasu Furukawa

IPC分类号： H01L23/66 ,  H01L23/049 ,  H01L23/492 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00 ,  H01Q1/22 ,  H01Q1/48

CPC分类号： H01L23/66 ,  H01L21/4817 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4875 ,  H01L23/04 ,  H01L23/041 ,  H01L23/043 ,  H01L23/049 ,  H01L23/055 ,  H01L23/492 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15192 ,  H01L2924/16195 ,  H01Q1/2283 ,  H01Q1/48 ,  H01L2924/00014

摘要： A radio frequency circuit includes, a multilayer substrate having a grounded base metal and a plurality of insulating layers and wiring layers formed over the grounded base metal and having a recess surrounded by the plurality of insulating layers and wiring layers over the grounded base metal, an upper substrate having a through-hole penetrating the upper substrate, a first semiconductor chip mounted on the upper surface of the upper substrate and electrically coupled to a metal film formed on the lower surface of the upper substrate, a metal pillar formed on the upper surface of the grounded base metal in the recess, and a solder buried in the through-hole and bonded to the metal film and the upper surface of the metal pillar. The metal film is bonded to a ground wiring layer electrically coupled to the grounded base metal among the plurality of wiring layers.

公开(公告)号：US20180138132A1

公开(公告)日：2018-05-17

申请号：US15735858

申请日：2016-03-02

申请人： Mitsubishi Electric Corporation

发明人： Koichiro NISHIZAWA ,  Takayuki HISAKA

IPC分类号： H01L23/00 ,  H01L23/04 ,  H01L23/48 ,  H01L23/10 ,  H01L21/48 ,  H01L21/768

CPC分类号： H01L23/562 ,  H01L21/4817 ,  H01L21/76898 ,  H01L23/02 ,  H01L23/04 ,  H01L23/041 ,  H01L23/10 ,  H01L23/12 ,  H01L23/14 ,  H01L23/481 ,  H01L23/544 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2924/13051 ,  H01L2924/13064 ,  H01L2924/3025 ,  H01L2924/35121 ,  H01L2224/81

摘要： Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like. A hollow portion 9 in which the semiconductor circuit 3 is housed in an airtight state is provided between the device substrate 2 and the cap substrate 8. The bump portion 14 connects all the via portions 10 and the cap substrate 8. Thus, the via portions 10 can be reinforced using the bump portion 14A.

公开(公告)号：US09805995B2

公开(公告)日：2017-10-31

申请号：US15111238

申请日：2015-01-23

申请人： KYOCERA Corporation

发明人： Yoshiki Kawazu

IPC分类号： H05K5/00 ,  H01L23/04 ,  H01L23/057 ,  H01L23/14 ,  H01L23/552 ,  H01R24/38 ,  H01R103/00

CPC分类号： H01L23/041 ,  H01L23/057 ,  H01L23/142 ,  H01L23/552 ,  H01L2924/0002 ,  H01R24/38 ,  H01R2103/00 ,  H05K5/0069 ,  H05K5/0091 ,  H01L2924/00

摘要： An element-accommodating package which can improve frequency characteristics of an element-accommodating package having a coaxial connector, and a mounting structure are provided. An element-accommodating package includes a metallic substrate, a frame, a first coaxial connector, a second coaxial connector, and a circuit board. A groove is provided between one side of the frame and a side surface of the circuit board and between a first signal line and a second signal line.

公开(公告)号：US20170294362A1

公开(公告)日：2017-10-12

申请号：US15630112

申请日：2017-06-22

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Yusheng LIN ,  Chee Hiong CHEW ,  Francis J. CARNEY

IPC分类号： H01L23/055 ,  H01R4/48 ,  H01L23/50 ,  H01L23/10 ,  H01L23/057

CPC分类号： H01L23/055 ,  H01L21/50 ,  H01L23/041 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/4006 ,  H01L23/492 ,  H01L23/49811 ,  H01L23/49844 ,  H01L23/49861 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/72 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/72 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01R4/4863 ,  H01R4/489 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

公开(公告)号：US20170194296A1

公开(公告)日：2017-07-06

申请号：US15231444

申请日：2016-08-08

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Katsuhiro YASUI

IPC分类号： H01L25/07 ,  H01L23/04 ,  H01L23/00 ,  H01L23/29 ,  H01L25/00

CPC分类号： H01L25/072 ,  H01L23/041 ,  H01L23/053 ,  H01L23/24 ,  H01L23/28 ,  H01L23/29 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48227 ,  H01L2224/49052 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/85399

摘要： A semiconductor module includes an insulating substrate. A first and a second metal member are joined respectively to a side surface of the substrate. Each metal member has an opening formed therein. A first and a second conductive layer are on the upper surface of the substrate and spaced apart from each other. A first semiconductor chip is mounted on the first conductive layer. A first electrode of the first semiconductor chip is electrically connected to the first conductive layer, and a second electrode is electrically connected to the second conductive layer. A first terminal is electrically connected to the first conductive layer, and a second terminal is electrically connected to the second conductive layer. A sealing resin is disposed on the upper surface of the substrate to cover the first conductive layer, the second conductive layer, the first semiconductor chip, and portions of the first and second terminals.

公开(公告)号：US20160343683A1

公开(公告)日：2016-11-24

申请号：US15230076

申请日：2016-08-05

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Yusheng LIN ,  Chee Hiong CHEW ,  Francis J. CARNEY

IPC分类号： H01L23/00 ,  H01L23/492 ,  H01L23/498 ,  H01L23/04

CPC分类号： H01L23/055 ,  H01L21/50 ,  H01L23/041 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/4006 ,  H01L23/492 ,  H01L23/49811 ,  H01L23/49844 ,  H01L23/49861 ,  H01L23/50 ,  H01L24/45 ,  H01L24/72 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/72 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01R4/4863 ,  H01R4/489 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor package includes: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die. The pin includes a reversibly elastically deformable lower portion, which in implementations includes a spring, configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate. The pin is fixedly coupled in a top of the housing and is configured to be coupled with the substrate by lowering the housing towards the substrate. In implementations the pin includes two rigid portions coupled together only with a coil spring, the spring biasing the rigid portions away from one another when the housing is lowered towards the substrate.