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公开(公告)号：US11876486B1
公开(公告)日：2024-01-16
申请号：US18154968
申请日：2023-01-16
Applicant: NXP B.V.
Inventor： Siyaram Sahu , Anand Kumar Sinha , Ateet Omer , Krishna Thakur
CPC classification number: H03B5/06 , H03B5/362 , H03B5/366 , H03B2200/0062 , H03B2200/0082
Abstract: A low power crystal oscillator is provided. The crystal oscillator includes a gain stage circuit having a first gain stage input coupled at a first oscillator terminal and configured to receive a first oscillator signal of a crystal. A first bias circuit is configured to generate a first bias voltage based on the first oscillator signal. A reference circuit is configured to generate a reference current based on the first bias voltage. A comparator circuit is configured to generate a clock signal based on the first oscillator signal and the first bias voltage. The comparator circuit includes a second bias circuit configured to generate a second bias voltage. The gain stage circuit includes a second gain stage input coupled to receive the second bias voltage.
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公开(公告)号：US20240377855A1
公开(公告)日：2024-11-14
申请号：US18485562
申请日：2023-10-12
Applicant: NXP B.V.
Inventor： Siyaram Sahu , Anand Kumar Sinha , Krishna Thakur
Abstract: A clock generator includes a buffer stage to drive an output clock and a slew accelerator circuit to receive a first clock signal and generate an input clock signal to the buffer stage. The slew accelerator circuit includes first, second, and third inverter stages. The first stage generates a pair of non-overlapping clock signals from the first clock signal. A rise time of a first non-overlapping clock signal of the pair is faster than a rise time of a second non-overlapping clock signal of the pair, and a fall time of the second non-overlapping clock signal is faster than a fall time of the first non-overlapping clock signal. The second stage generates a first intermediate clock signal based on the pair of non-overlapping clock signals. The third stage generates the input clock signal to the buffer stage based on the first intermediate clock signal and the pair of non-overlapping clocks.
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公开(公告)号：US12113520B2
公开(公告)日：2024-10-08
申请号：US18180581
申请日：2023-03-08
Applicant: NXP B.V.
Inventor： Saurabh Goyal , Krishna Thakur
IPC: H03K17/16
CPC classification number: H03K17/161
Abstract: A bootstrap switch circuit includes a transistor-based switch controlled by a first gate signal and a leakage protection transistor controlled by a second gate signal configured to reduce gate induced drain leakage in the transistor-based switch A first gate driver is included that produces a first gate signal at its output so that the first gate signal turns on the transistor-based switch during a sampling mode and turns off the transistor-based switch during a hold mode. A second gate driver is included that produces a second gate signal at its output and to receive the output signal of the bootstrap switch circuit so that the second gate signal turns on the leakage protection transistor during the sampling mode and turns off the leakage protection transistor during the hold mode and the second gate signal is based upon the output signal of the bootstrap switch circuit.
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公开(公告)号：US20250055446A1
公开(公告)日：2025-02-13
申请号：US18771327
申请日：2024-07-12
Applicant: NXP B.V.
Inventor： Vishwajit Babasaheb Bugade , Anand Kumar Sinha , Krishna Thakur , Siyaram Sahu
Abstract: A method for quadrature phase shifted clock generation with duty cycle correction includes A reference clock is delayed with a delay circuit to generate a delayed clock, wherein a delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock comprise a plurality of states comprising a first state and a second state. A first edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. A second edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. The control value is driven to the first edge value during the second state of the delayed clock and to the second edge value during the first state of the delayed clock.
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公开(公告)号：US12191859B2
公开(公告)日：2025-01-07
申请号：US18332042
申请日：2023-06-09
Applicant: NXP B.V.
Inventor： Saurabh Goyal , Divya Tripathi , Krishna Thakur , Deependra Kumar Jain
Abstract: An integrated circuit including a functional circuit, a tuning circuit, and a control circuit is provided. The functional and control circuits generate an output signal and a digital code, respectively. The tuning circuit tunes the functional circuit based on the digital code to control an attribute of the output signal. The digital code is iteratively adjusted such that the attribute of the output signal is maintained within a predefined range. When the digital code corresponds to a cliff value, the digital code for a subsequent iteration is adjusted by a non-unit offset value such that a difference between the attribute for the cliff value and for the subsequent digital code is within a tolerance limit. The digital code is indicative of coarse and fine parameters, and for each value of the coarse parameter, the cliff value corresponds to the lowest or highest value of the fine parameter.
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Patent Agency Ranking
公开(公告)号：US20240192720A1
公开(公告)日：2024-06-13
申请号：US18168622
申请日：2023-02-14
Applicant: NXP B.V.
Inventor： Vishwajit Babasaheb Bugade , Anand Kumar Sinha , Krishna Thakur , Siyaram Sahu
CPC classification number: G06F1/08 , H03K5/01 , H03K2005/00013
Abstract: A phase shifted clock generator that includes a delay circuit, a capacitor, and a control circuit is provided. The delay circuit receives a reference clock signal and generates a phase shifted clock signal. A phase difference between the phase shifted clock signal and the reference clock signal is controlled based on a delay of the delay circuit. The control circuit controls, based on the phase shifted clock signal and the reference clock signal, a control voltage generated at the capacitor. The control circuit controls the control voltage by charging and discharging the capacitor with a constant current. The delay of the delay circuit is controlled based on the control voltage such that the phase difference between the phase shifted clock signal and the reference clock signal is within a predefined range.
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公开(公告)号：US11601130B2
公开(公告)日：2023-03-07
申请号：US17304628
申请日：2021-06-23
Applicant: NXP B.V.
Inventor： Gaurav Agrawal , Deependra Kumar Jain , Krishna Thakur
Abstract: An initialization circuit of a delay locked loop (DLL) includes a sense circuit and a control circuit. The sense circuit receives an enable signal, a reference clock signal, and various delayed reference clock signals, and outputs another enable signal. The control circuit receives the two enable signals and outputs and provides a control signal to a loop filter of the DLL to control a delay value associated with the DLL. The control signal is provided to the loop filter such that the delay value associated with the DLL equals a predetermined delay value for a predetermined time duration. Further, after a lapse of the predetermined time duration, the delay value associated with the DLL increases until a difference between a time period of the reference clock signal and the delay value equals a threshold value.
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公开(公告)号：US12164326B2
公开(公告)日：2024-12-10
申请号：US18168622
申请日：2023-02-14
Applicant: NXP B.V.
Inventor： Vishwajit Babasaheb Bugade , Anand Kumar Sinha , Krishna Thakur , Siyaram Sahu
Abstract: A phase shifted clock generator that includes a delay circuit, a capacitor, and a control circuit is provided. The delay circuit receives a reference clock signal and generates a phase shifted clock signal. A phase difference between the phase shifted clock signal and the reference clock signal is controlled based on a delay of the delay circuit. The control circuit controls, based on the phase shifted clock signal and the reference clock signal, a control voltage generated at the capacitor. The control circuit controls the control voltage by charging and discharging the capacitor with a constant current. The delay of the delay circuit is controlled based on the control voltage such that the phase difference between the phase shifted clock signal and the reference clock signal is within a predefined range.
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公开(公告)号：US20240213978A1
公开(公告)日：2024-06-27
申请号：US18180581
申请日：2023-03-08
Applicant: NXP B.V.
Inventor： Saurabh Goyal , Krishna Thakur
IPC: H03K17/16
CPC classification number: H03K17/161
Abstract: A bootstrap switch circuit includes a transistor-based switch controlled by a first gate signal and a leakage protection transistor controlled by a second gate signal configured to reduce gate induced drain leakage in the transistor-based switch A first gate driver is included that produces a first gate signal at its output so that the first gate signal turns on the transistor-based switch during a sampling mode and turns off the transistor-based switch during a hold mode. A second gate driver is included that produces a second gate signal at its output and to receive the output signal of the bootstrap switch circuit so that the second gate signal turns on the leakage protection transistor during the sampling mode and turns off the leakage protection transistor during the hold mode and the second gate signal is based upon the output signal of the bootstrap switch circuit.
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公开(公告)号：US20240204757A1
公开(公告)日：2024-06-20
申请号：US18332042
申请日：2023-06-09
Applicant: NXP B.V.
Inventor： Saurabh Goyal , Divya Tripathi , Krishna Thakur , Deependra Kumar Jain
CPC classification number: H03K3/017 , H03K3/0315 , H03K5/135
Abstract: An integrated circuit including a functional circuit, a tuning circuit, and a control circuit is provided. The functional and control circuits generate an output signal and a digital code, respectively. The tuning circuit tunes the functional circuit based on the digital code to control an attribute of the output signal. The digital code is iteratively adjusted such that the attribute of the output signal is maintained within a predefined range. When the digital code corresponds to a cliff value, the digital code for a subsequent iteration is adjusted by a non-unit offset value such that a difference between the attribute for the cliff value and for the subsequent digital code is within a tolerance limit. The digital code is indicative of coarse and fine parameters, and for each value of the coarse parameter, the cliff value corresponds to the lowest or highest value of the fine parameter.
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