公开(公告)号：US20250142923A1

公开(公告)日：2025-05-01

申请号：US18499088

申请日：2023-10-31

Applicant: NXP USA, Inc.

Inventor： Bernhard Grote ,  Bruce McRae Green

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor device includes a semiconductor substrate, surface passivation over the semiconductor substrate, and a first interlayer dielectric over the surface passivation. A gate electrode includes a gate channel portion that extends through the surface passivation to contact the upper surface of the semiconductor substrate, a first gate field plate with a first horizontal bottom extent that overlies and contacts the upper surface of the surface passivation, and a second gate field plate with a second horizontal bottom extent that is higher than the first horizontal bottom extent. A conductive field plate includes a first field plate with a third horizontal bottom extent that is recessed below the upper surface of the surface passivation, and a second field plate with a fourth horizontal bottom extent that is higher than the first horizontal bottom extent of the first gate field plate.

公开(公告)号：US20250142922A1

公开(公告)日：2025-05-01

申请号：US18499083

申请日：2023-10-31

Applicant: NXP USA, Inc.

Inventor： Bernhard Grote ,  Bruce McRae Green

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, surface passivation over the semiconductor substrate, and a first interlayer dielectric over the surface passivation. A gate electrode includes a gate channel portion that extends through the surface passivation to contact the upper surface of the semiconductor substrate, a first gate field plate with a first horizontal bottom extent that overlies the upper surface of the surface passivation, and a second gate field plate with a second horizontal bottom extent that is higher than the first horizontal bottom extent. A conductive field plate includes a first field plate with a third horizontal bottom extent that overlies and contacts the upper surface of the surface passivation, and a second field plate with a fourth horizontal bottom extent that is at least as high as the first horizontal bottom extent of the first gate field plate.

公开(公告)号：US20240395872A1

公开(公告)日：2024-11-28

申请号：US18324108

申请日：2023-05-25

Applicant: NXP USA, Inc.

Inventor： Jie Hu ,  Bernhard Grote

IPC: H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor device includes a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate, a passivation layer between the source and drain electrodes, a gate electrode between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends at least partially through the passivation layer. The conductive field plate includes a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer. The conductive field plate and the upper surface of the semiconductor substrate are separated by a portion of the lower passivation sub-layer.

公开(公告)号：US20240222442A1

公开(公告)日：2024-07-04

申请号：US18147972

申请日：2022-12-29

Applicant: NXP USA, Inc.

Inventor： Bernhard Grote ,  Jie Hu ,  Philippe Renaud ,  Congyong Zhu ,  Bruce McRae Green

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/401 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/205

Abstract: A semiconductor device includes a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate, a passivation layer between the source and drain electrodes, a gate electrode between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends at least partially through the passivation layer. The conductive field plate includes a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer. The conductive field plate and the upper surface of the semiconductor substrate are separated by a portion of the lower passivation sub-layer.

公开(公告)号：US11777002B2

公开(公告)日：2023-10-03

申请号：US17457801

申请日：2021-12-06

Applicant: NXP USA, INC.

Inventor： Saumitra Raj Mehrotra ,  Bernhard Grote ,  Ljubo Radic

IPC: H01L29/40 ,  H01L29/10 ,  H01L29/45 ,  H01L29/66 ,  H01L21/765 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L29/1095 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66704 ,  H01L29/7825

Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A gate region includes a conductive material filled in the trench. A drift region having a first conductivity type is formed in the semiconductor substrate adjacent to the second sidewall. A drain region is formed in the drift region and separated from the second sidewall by a first distance. A dielectric layer is formed at the top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region. A field plate is formed over the dielectric layer and isolated from the conductive material and the drift region by way of the dielectric layer.

公开(公告)号：US20230207675A1

公开(公告)日：2023-06-29

申请号：US17561793

申请日：2021-12-24

Applicant: NXP USA, INC.

Inventor： Bernhard Grote ,  Humayun Kabir ,  Bruce McRae Green ,  Ibrahim Khalil

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/42376 ,  H01L29/402 ,  H01L29/66462

Abstract: A semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, a second dielectric layer disposed over the first dielectric layer, a third dielectric layer disposed over the second dielectric layer, a lower opening formed in the first dielectric layer, an upper opening formed in the second dielectric layer and the third dielectric layer, wherein at least a portion of the upper opening overlaps a portion of the lower opening, and a control electrode formed within at least a portion of the lower opening and within a portion of the upper opening, wherein a portion of the control electrode is formed over the third dielectric layer.

公开(公告)号：US11217675B2

公开(公告)日：2022-01-04

申请号：US16836344

申请日：2020-03-31

Applicant: NXP USA, INC.

Inventor： Saumitra Raj Mehrotra ,  Bernhard Grote ,  Ljubo Radic

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor device includes a trench in a semiconductor material having a device section and a termination section. A gate structure is located in the trench. With some embodiments, the transverse cross-sectional width of the termination section is wider than the transverse cross-sectional width of the device section.

公开(公告)号：US20210159323A1

公开(公告)日：2021-05-27

申请号：US16692517

申请日：2019-11-22

Applicant: NXP USA, INC.

Inventor： Saumitra Raj Mehrotra ,  Ljubo Radic ,  Bernhard Grote

IPC: H01L29/66 ,  H01L29/40 ,  H01L27/088 ,  H01L29/78

Abstract: Disclosed herein is a transistor structure that is formed by forming a sidewall spacer along a first vertical component sidewall of a trench wherein no sidewall spacer is formed along a second vertical component sidewall of the trench. During an etching of a dielectric layer in the trench, the sidewall spacer protects a first portion of the dielectric layer from being etched while a second portion of the dielectric layer along the second sidewall is etched. A portion of a control terminal can be formed in the space where the second portion is removed.

公开(公告)号：US10749028B2

公开(公告)日：2020-08-18

申请号：US16205461

申请日：2018-11-30

Applicant: NXP USA, INC.

Inventor： Saumitra Raj Mehrotra ,  Bernhard Grote ,  Ljubo Radic

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/66

Abstract: Disclosed herein is a conductive structure that serves as both a control terminal and a field plate for a transistor. The transistor includes a channel region including a portion located in a vertical sidewall of semiconductor material that separates an upper level portion and a lower level portion of the semiconductor material. An extended drain region includes a portion located in the lower portion of the semiconductor material. The conductive structure is laterally adjacent to the vertical sidewall and includes a first vertical side and an opposite second vertical side with the first vertical side being closer to the vertical component sidewall. The first side is vertically closer to the lower level portion of the semiconductor material than the second vertical side.

公开(公告)号：US20200135896A1

公开(公告)日：2020-04-30

申请号：US16171830

申请日：2018-10-26

Applicant: NXP USA, INC.

Inventor： Bernhard Grote ,  Ljubo Radic ,  Saumitra Raj Mehrotra ,  Tania Tricia-Marie Thomas ,  Mark Edward Gibson

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40 ,  H01L21/22

Abstract: A method of forming a transistor device where an extended drain region is formed by performing angled ion implantation of conductivity dopants of a first conductivity type into the sidewalls and bottom portion of a trench. The bottom portion of the trench is then implanted with dopants of a second conductivity type. Source and drain regions are formed on opposing sides of the trench including in upper portions of the trench sidewalls. A channel region is formed in a trench sidewall below the source region. The trench includes a control terminal structure. After formation of the transistor device, the net conductivity type of the bottom portion of the trench is of the first conductivity type.