-
公开(公告)号:US10216663B2
公开(公告)日:2019-02-26
申请号:US15395236
申请日:2016-12-30
Applicant: NXP USA, INC.
Inventor: Amir D. Modan , Ron Michael Bar , Thomas Riesenberg
Abstract: A processing system includes a general purpose instruction based data processor, an input configured to receive a command written by the data processor, a timer manager controller configured to receive the command and to execute the command, and a debug interrupt timer controller (DITC) configured to determine that the command is directed to the DITC and to store configuration information that associates the command with an element of the processing system that is a source of the command, where the configuration information is included in the command.
-
公开(公告)号:US20180165118A1
公开(公告)日:2018-06-14
申请号:US15373208
申请日:2016-12-08
Applicant: NXP USA, INC.
Inventor: Ron Michael Bar , Eran Glickman , Hezi Rahamim
CPC classification number: G06F9/4825
Abstract: A processing system includes a data processor, an input, an output, a memory, an operation parser, and a timer manager instance controller. The input receives create-timer-manager-instance (CTMI) commands identifying a number of timers supported by a timer manager instance. The output provides responses including a CTMI response associated with the CTMI command. The operation parser receives the CTMI command from the input. The timer manager instance controller receive a control input from the operation parser based upon the CTMI command, and in response, allocates a block of memory locations in the memory based on the number of timers and provides a CTMI response to the output to indicate that the CTMI response was executed by the timer manager instance controller.
-
公开(公告)号:US20180189208A1
公开(公告)日:2018-07-05
申请号:US15395236
申请日:2016-12-30
Applicant: NXP USA, INC.
Inventor: Amir D. Modan , Ron Michael Bar , Thomas Riesenberg
CPC classification number: G06F13/24 , G06F9/4825 , G06F11/0757
Abstract: A processing system includes a general purpose instruction based data processor, an input configured to receive a command written by the data processor, a timer manager controller configured to receive the command and to execute the command, and a debug interrupt timer controller (DITC) configured to determine that the command is directed to the DITC and to store configuration information that associates the command with an element of the processing system that is a source of the command, where the configuration information is included in the command.
-
-