公开(公告)号：US20250112627A1

公开(公告)日：2025-04-03

申请号：US18891369

申请日：2024-09-20

Applicant: NXP USA, Inc.

Inventor： Nihaar N. Mahatme ,  Srikanth Jagannathan ,  Akhilesh Kumar Singh ,  Girraj Kumar Agrawal

IPC: H03K5/19 ,  H03K5/14 ,  H03L7/093

Abstract: In a system on a chip (SoC), clock selection circuitry provides a selected one of a first or second clock signal as an output clock based on at least one of a first flag and a second flag. This output clock is provided as a reference clock to one or more phase locked loops (PLLs) of the SoC. The SoC includes a first clock path which receives a first oscillating signal from a first clock source external to the SoC to generate the first clock signal, and a second clock path which receives a second oscillating signal from a second clock source external to the SoC to generate the second clock signal. A first glitch monitor asserts the first flag when a glitch is detected in the first oscillating signal, and a second glitch monitor configured asserts the second flag when a glitch is detected in the second oscillating signal.