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公开(公告)号：US20240321372A1
公开(公告)日：2024-09-26
申请号：US18188804
申请日：2023-03-23
Applicant: NXP USA, Inc.
Inventor： Anirban Roy , Nihaar N. Mahatme , Jon Scott Choy
Abstract: A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.
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公开(公告)号：US11233663B1
公开(公告)日：2022-01-25
申请号：US16935439
申请日：2020-07-22
Applicant: NXP USA, Inc.
Inventor： Alexander Hoefler , Glenn Charles Abeln , Brad John Garni , Nihaar N. Mahatme
Abstract: A physically unclonable function (PUF) includes an array of differential PUF bits arranged in rows and columns, wherein each differential bit is located at an intersection of a row and a column, and includes a first PUF cell coupled to a corresponding first bit line and first source line and a second PUF cell coupled to a corresponding second bit line and second source line. The PUF includes a source bias transistor coupled between each corresponding first source line and a first power supply terminal and between each corresponding second source line and the first power supply terminal, wherein a gate electrode of each of the source bias transistors is coupled to a second power supply terminal, and a corresponding set of margin transistors coupled in parallel with each source bias transistor, wherein a gate electrode of each margin transistor is coupled to receive a corresponding margin setting control signal.
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公开(公告)号：US20210027814A1
公开(公告)日：2021-01-28
申请号：US16523284
申请日：2019-07-26
Applicant: NXP USA, INC.
Inventor： Nihaar N. Mahatme , Alexander Hoefler , Brad John Garni
IPC: G11C7/12 , G11C11/419 , G11C11/418 , G11C7/18 , H04L9/32
Abstract: A data processing system and method for generating a digital code for use as a physically unclonable function (PUF) response is provided. The method includes activating a plurality of word lines for a read operation. A first bit line is coupled to a first input of a comparator during the read operation. A second bit line is coupled to a second input of the comparator during the read operation. A current is generated on each of the first and second bit lines. The currents on the first and second bit lines are converted to voltages. The voltage on the first bit line is compared to the voltage on the second bit line. A logic bit is output from the comparator as part of the digital code, a logic state of the logic bit is determined in response to the comparison. By selecting multiple word lines to determine a PUF response, noise immunity is improved.
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公开(公告)号：US20200379063A1
公开(公告)日：2020-12-03
申请号：US16427478
申请日：2019-05-31
Applicant: NXP USA, Inc.
Inventor： Nihaar N. Mahatme , Mehul D. Shroff
IPC: G01R33/07 , G11C14/00 , G11C11/155 , G11C11/16
Abstract: An integrated circuit includes a magneto resistive RAM (MRAM) array having a plurality of MRAM cells, and a set of at least one Hall sensor circuit, each of the set including a Hall sensor to detect a magnetic field. The integrated circuit also includes magnetic processing circuitry for receiving at least one indication from the set of at least one Hall sensor circuit. The magnetic processing circuitry including an output to provide an indication of a possible magnetic field threat to the MRAM array based on the at least one indication from the set.
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公开(公告)号：US10574469B1
公开(公告)日：2020-02-25
申请号：US16380274
申请日：2019-04-10
Applicant: NXP USA, INC.
Inventor： Brad John Garni , Nihaar N. Mahatme , Alexander Hoefler
IPC: H04L9/32 , G06F3/06 , G11C11/41 , H03K19/0944 , G06F12/14 , G11C11/418 , G11C11/419
Abstract: A physically unclonable function (PUF) is implemented using a PUF array of single-transistor cells organized as a plurality of word lines and intersecting bit lines. A single-transistor cell is connected to a word line and bit line at each of the intersections. A current source is coupled to each of the bit lines and provides a current when a PUF cell connected to the bit line is conductive. The bit lines are organized in pairs. A PUF evaluation engine is coupled to the PUF array and provides an address for selecting a word line of the PUF array in response to a challenge. A comparator is coupled to each pair of bit lines of the PUF array for detecting a current. The comparator provides a voltage signal in response to detecting a difference current between the first and second bit line. The PUF evaluation engine receives the voltage signal and generates a logic bit.
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Patent Agency Ranking
公开(公告)号：US12001674B2
公开(公告)日：2024-06-04
申请号：US18050547
申请日：2022-10-28
Applicant: NXP USA, Inc.
Inventor： Nihaar N. Mahatme , Anirban Roy
IPC: G06F3/00 , G06F3/06 , G06F9/4401 , G11C11/412 , G11C11/419
CPC classification number: G06F3/0604 , G06F3/0632 , G06F3/0679 , G06F9/4401 , G11C11/4125 , G11C11/419
Abstract: An array of bit cells is programmed with user data, each row including a corresponding word line and each column including a corresponding column line. The array includes a plurality of differential PUF bits, each having a first and second bit cell programmed with user data. A first set of sense-amplifiers outputs a set of data bits of the user data, and a second set of sense-amplifiers outputs a set of differential bits, each differential bit based on a differential current between two columns lines of the selected column lines corresponding to the first and second bit cells of a corresponding differential PUF bit along the selected word line. A potential PUF bit generator outputs a set of potential PUF bits based on the set of data bits of the user data from the first set of sense-amplifiers and the set of differential bits from the second set of sense-amplifiers.
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公开(公告)号：US20240143167A1
公开(公告)日：2024-05-02
申请号：US18050547
申请日：2022-10-28
Applicant: NXP USA, Inc.
Inventor： Nihaar N. Mahatme , Anirban Roy
IPC: G06F3/06 , G06F9/4401 , G11C11/412 , G11C11/419
CPC classification number: G06F3/0604 , G06F3/0632 , G06F3/0679 , G06F9/4401 , G11C11/4125 , G11C11/419
Abstract: An array of bit cells is programmed with user data, each row including a corresponding word line and each column including a corresponding column line. The array includes a plurality of differential PUF bits, each having a first and second bit cell programmed with user data. A first set of sense-amplifiers outputs a set of data bits of the user data, and a second set of sense-amplifiers outputs a set of differential bits, each differential bit based on a differential current between two columns lines of the selected column lines corresponding to the first and second bit cells of a corresponding differential PUF bit along the selected word line. A potential PUF bit generator outputs a set of potential PUF bits based on the set of data bits of the user data from the first set of sense-amplifiers and the set of differential bits from the second set of sense-amplifiers.
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公开(公告)号：US20220179740A1
公开(公告)日：2022-06-09
申请号：US17247376
申请日：2020-12-09
Applicant: NXP USA, Inc.
Inventor： Anirban Roy , Nihaar N. Mahatme
Abstract: A magnetoresistive random-access memory (MRAM) device includes an array of MRAM bit cells grouped into words, each word having specified number of data bit cells, error correction code (ECC) bit cells, and at least two inversion indicator bit cells, the inversion indicator bit cells being redundant of each other; and a memory controller. The memory controller is configured to, for each of the words, set the inversion indicator bit cells to indicate whether the number of data bit cells in a word having a zero value is greater than the number of data bit cells having a one value, invert the zeroes and ones in the bit cells when the inversion indicator bit cells are set to indicate a greater number of zeroes than ones in the data bit cells of the word, and revert the data bit cells to their value before the zeroes and ones were inverted.
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公开(公告)号：US11222679B2
公开(公告)日：2022-01-11
申请号：US16573075
申请日：2019-09-17
Applicant: NXP USA, Inc.
Inventor： Nihaar N. Mahatme , Mehul D. Shroff
Abstract: A packaged integrated circuit includes a photodiode and a memory. The photodiode generates energy when radiation strikes a surface of the photodiode. The memory includes a plurality of non-volatile memory cells and memory control circuitry. The memory control circuitry is configured to perform an operation to change values stored in at least some of the memory cells of the plurality of non-volatile memory cells while being powered by energy generated by the photodiode. An encapsulant at least partially encapsulates the photodiode and the memory, in which the encapsulant blocks radiation from reaching the surface of the photodiode.
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公开(公告)号：US10446225B1
公开(公告)日：2019-10-15
申请号：US15966390
申请日：2018-04-30
Applicant: NXP USA, INC.
Inventor： Alexander Hoefler , Nihaar N. Mahatme
IPC: G11C11/00 , G11C11/417 , G11C11/412
Abstract: A memory system includes an isolated first well of a first polarity and an array of volatile memory cells. Each of the memory cells includes a first set of transistors in the isolated first well, and a second set of transistors. A source bias circuit is coupled to the array of volatile memory cells. At least a portion of the source bias circuit is in the isolated first well and coupled to source electrodes of the first set of transistors of each of the memory cells. A control circuit is configured to enable the source bias circuit.
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