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    CLOCK GENERATION WITH GLITCH DETECTION AND HANDLING
    1.
    发明申请
    CLOCK GENERATION WITH GLITCH DETECTION AND HANDLING 有权

    公开(公告)号：US20250112627A1

    公开(公告)日：2025-04-03

    申请号：US18891369

    申请日：2024-09-20

    Applicant: NXP USA, Inc.

    Inventor： Nihaar N. Mahatme ,  Srikanth Jagannathan ,  Akhilesh Kumar Singh ,  Girraj Kumar Agrawal

    IPC: H03K5/19 ,  H03K5/14 ,  H03L7/093

    Abstract: In a system on a chip (SoC), clock selection circuitry provides a selected one of a first or second clock signal as an output clock based on at least one of a first flag and a second flag. This output clock is provided as a reference clock to one or more phase locked loops (PLLs) of the SoC. The SoC includes a first clock path which receives a first oscillating signal from a first clock source external to the SoC to generate the first clock signal, and a second clock path which receives a second oscillating signal from a second clock source external to the SoC to generate the second clock signal. A first glitch monitor asserts the first flag when a glitch is detected in the first oscillating signal, and a second glitch monitor configured asserts the second flag when a glitch is detected in the second oscillating signal.

    Packaged semiconductor device assembly
    2.
    发明授权
    Packaged semiconductor device assembly 有权

    公开(公告)号：US11908784B2

    公开(公告)日：2024-02-20

    申请号：US17029680

    申请日：2020-09-23

    Applicant: NXP USA, Inc.

    Inventor： Akhilesh Kumar Singh ,  Andrew Jefferson Mawer ,  Nishant Lakhera ,  Chee Seng Foong ,  Nihaar N. Mahatme

    IPC: H01L23/498 ,  H01L23/00 ,  H01L21/52

    CPC classification number: H01L23/49833 ,  H01L21/52 ,  H01L23/49811 ,  H01L24/73 ,  H01L2224/73265

    Abstract: A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.

    HYBRID PACKAGE
    3.
    发明申请
    HYBRID PACKAGE 审中-公开

    公开(公告)号：US20200185319A1

    公开(公告)日：2020-06-11

    申请号：US16791817

    申请日：2020-02-14

    Applicant: NXP USA, Inc.

    Inventor： Akhilesh Kumar Singh ,  Nishant Lakhera ,  Chee Seng Foong

    IPC: H01L23/498 ,  H01L21/48

    Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.

    Hybrid package
    4.
    发明授权
    Hybrid package 有权

    公开(公告)号：US11189557B2

    公开(公告)日：2021-11-30

    申请号：US16791817

    申请日：2020-02-14

    Applicant: NXP USA, Inc.

    Inventor： Akhilesh Kumar Singh ,  Nishant Lakhera ,  Chee Seng Foong

    IPC: H01L23/498 ,  H01L21/48

    Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.

    HYBRID PACKAGE
    5.
    发明申请
    HYBRID PACKAGE 审中-公开

    公开(公告)号：US20200013711A1

    公开(公告)日：2020-01-09

    申请号：US16030108

    申请日：2018-07-09

    Applicant: NXP USA, Inc.

    Inventor： Akhilesh Kumar Singh ,  Nishant Lakhera ,  Chee Seng Foong

    IPC: H01L23/498 ,  H01L21/48

    Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.

    PACKAGED SEMICONDUCTOR DEVICE ASSEMBLY
    7.
    发明申请
    PACKAGED SEMICONDUCTOR DEVICE ASSEMBLY 有权

    公开(公告)号：US20220093499A1

    公开(公告)日：2022-03-24

    申请号：US17029680

    申请日：2020-09-23

    Applicant: NXP USA, Inc.

    Inventor： Akhilesh Kumar Singh ,  Andrew Jefferson Mawer ,  Nishant Lakhera ,  Chee Seng Foong ,  Nihaar N. Mahatme

    IPC: H01L23/498 ,  H01L23/00 ,  H01L21/52

    Abstract: A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.

    Package with conductive underfill ground plane
    8.
    发明授权
    Package with conductive underfill ground plane 有权

    公开(公告)号：US11270972B2

    公开(公告)日：2022-03-08

    申请号：US16438546

    申请日：2019-06-12

    Applicant: NXP USA, Inc.

    Inventor： Nishant Lakhera ,  Akhilesh Kumar Singh ,  Chee Seng Foong

    IPC: H01L23/00 ,  H01L23/498

    Abstract: Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.

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