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公开(公告)号：US20250062760A1
公开(公告)日：2025-02-20
申请号：US18452365
申请日：2023-08-18
Applicant: NXP USA, Inc.
Inventor： Christopher James Micielli , Srikanth Jagannathan
IPC: H03K17/082 , H03K17/00
Abstract: A power switch includes a first transistor and a second transistor, coupled in series between a first power supply voltage and a pad. The power switch also includes an analog multiplexer (MUX). The MUX is configured to provide a pad voltage to a control electrode of the first transistor when an overvoltage (OV) condition is detected on the pad, a second power supply voltage to the control electrode of the first transistor when an undervoltage (UV) condition is detected on the pad, and a reference voltage to the control electrode of the first transistor when neither the UV condition nor the OV condition is detected on the pad. The first power supply voltage is greater than the second power supply voltage, and the reference voltage is a fraction of the first power supply voltage.
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公开(公告)号：US11196411B2
公开(公告)日：2021-12-07
申请号：US16270002
申请日：2019-02-07
Applicant: NXP USA, INC.
Inventor： Srikanth Jagannathan , Kumar Abhishek
Abstract: A circuit including a device including a first and second node. The device operating in at least an enabled mode and a disabled mode. The circuit including a voltage control circuit. The voltage control circuit including a current source for sourcing current to or sinking current from the first node during the disabled mode and a voltage difference detector including an output for providing an indication of a measured voltage difference between the first node and the second node. The voltage control circuit includes a current source control circuit including a first input to receive the indication of the measured voltage difference and an output to control current sourced to or sinked from the first node by the current source to limit a voltage difference between the first and second node based on a comparison between the indication of the measured voltage difference and an indication of a target voltage difference.
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公开(公告)号：US10680594B2
公开(公告)日：2020-06-09
申请号：US16030945
申请日：2018-07-10
Applicant: NXP USA, INC.
Inventor： Christopher James Micielli , Srikanth Jagannathan , Manmohan Rana , Carl Culshaw
Abstract: A comparator circuit includes a first transistor have a control electrode coupled to a first input voltage, a first current electrode coupled to a second input voltage, and a second current electrode coupled to a first circuit node. The circuit also includes a first inverter coupled to a first voltage supply terminal and having a first input coupled to the first circuit node and an output, a second transistor having a control electrode coupled to the output of the first inverter, and an active resistive element coupled in series between the first circuit node and a first current electrode of the second transistor.
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4.发明授权公开(公告)号：US10205441B1
公开(公告)日：2019-02-12
申请号：US15842293
申请日：2017-12-14
Applicant: NXP USA, INC.
Inventor： Kumar Abhishek , Srikanth Jagannathan
IPC: H03K5/003 , H03K19/003 , H03K3/356
Abstract: A level shifter includes a level shifting circuit, a variable bias voltage generator, and a bias voltage generator controller. The level shifting circuit is configured to level shift an input signal at a first voltage level to an output signal having a second voltage level. The second voltage level is higher than the first voltage level. The level shifting circuit includes a current mirror, an input circuit for receiving the differential input signals, and a coupling circuit for coupling the current mirror to the input circuit in response to a variable bias voltage. The variable bias voltage generator is configured to provide the variable bias voltage at one of a plurality of voltage levels. The bias voltage generator controller provides a select signal to select the voltage level from the plurality of voltage levels in response to measuring the duty cycle of the output signal to maintain the duty cycle of the output signal at a predetermined duty cycle.
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公开(公告)号：US09947391B1
公开(公告)日：2018-04-17
申请号：US15486049
申请日：2017-04-12
Applicant: NXP USA, INC.
Inventor： Nihaar N. Mahatme , Srikanth Jagannathan , Alexander Hoefler
IPC: G11C11/00 , G11C11/419 , G11C11/418
CPC classification number: G11C11/419 , G11C7/24 , G11C11/418 , G11C29/021 , G11C29/028
Abstract: A physically unclonable function (PUF) is implemented in a plurality of SRAM cells. In a method for generating a PUF response, a logic zero is first written to all the SRAM cells of the PUF. A bit line coupled to the storage node that stores the logic zero of each SRAM cell is biased to a predetermined voltage. The bit lines are then selected for an evaluation read operation. During the evaluation read, a read current of one of the bit lines from one column is converted to a first voltage and a read current of another bit line of another column is converted to a second voltage. The first voltage is then compared to the second voltage. A logic state of a bit of the PUF response is determined as a result of the comparison. The logic bit may be provided to the input of a parallel-in serial-out shift register. There may be a comparator for each logic bit, or a few comparators may be shared between the logic bits. The PUF response may be used to provide a signature for the data processing system. The back-bias of each cell may be selectively adjusted.
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Patent Agency Ranking
公开(公告)号：US11561255B2
公开(公告)日：2023-01-24
申请号：US17231642
申请日：2021-04-15
Applicant: NXP USA, Inc.
Inventor： Kumar Abhishek , Xiankun Jin , Srikanth Jagannathan
Abstract: An integrated circuit includes an input/output (I/O) circuit configured to receive a first signal and a second signal and a fault detection circuit. The I/O circuit includes an I/O terminal, an I/O buffer, and a pull resistor having a first terminal coupled to the I/O terminal. The fault detection circuit is configured to determine whether a predetermined number of toggles of the first signal occurs while the second signal is held at a constant logic state, assert a fault indicator when the predetermined number of toggles occurs, and negate the fault indicator when the predetermined number of toggles does not occur.
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公开(公告)号：US11047904B2
公开(公告)日：2021-06-29
申请号：US16292654
申请日：2019-03-05
Applicant: NXP USA, INC.
Inventor： Kumar Abhishek , Srikanth Jagannathan , Thomas Henry Luedeke , Venkannababu Ambati , Mark Shelton Cinque , Joseph Rollin Wright
IPC: G01R31/28
Abstract: An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generates an output signal indicative of an external terminal of the plurality of external terminal circuits being placed at a wakeup voltage. The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.
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公开(公告)号：US10955467B2
公开(公告)日：2021-03-23
申请号：US16223329
申请日：2018-12-18
Applicant: NXP USA, INC.
Inventor： Kumar Abhishek , Srikanth Jagannathan , Hector Sanchez
IPC: G01R31/28
Abstract: An embedded continuity test circuit is provided. An integrated circuit includes a bond pad and an oscillator circuit. The oscillator circuit is configured to generate an oscillator signal having a first frequency when the bond pad is coupled to a bond region of a package and a second frequency when the bond pad is not coupled to the bond region of the package.
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公开(公告)号：US10763880B1
公开(公告)日：2020-09-01
申请号：US16275647
申请日：2019-02-14
Applicant: NXP USA, INC.
IPC: H03M1/36
Abstract: An A/D converter includes multiple bin comparators that compare an analog voltage to corresponding bin threshold voltages to provide output signals for providing corresponding comparison results. Some of the comparators includes enable inputs that selectively enable the output signal of the bin comparator to provide the corresponding comparison result based on a corresponding comparison result from at least one other bin comparator. The A/D convertor includes an encoder that utilizes the output signals to provide encoded bit values of the digital output. The A/D converter includes a bin selection circuit that utilizes the output signals to select a voltage level based on the output signals and provides the selected voltage level to a next stage of the A/D convertor. The next stage uses the selected voltage level and the analog voltage to provide at least one lessor bit of the digital output.
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公开(公告)号：US10013042B1
公开(公告)日：2018-07-03
申请号：US15655063
申请日：2017-07-20
Applicant: NXP USA, Inc.
Inventor： Kumar Abhishek , Srikanth Jagannathan
CPC classification number: G06F1/3225 , G06F1/263 , G06F1/28 , G06F1/3275 , G11C5/04 , G11C5/141 , G11C5/143 , G11C8/18
Abstract: A memory system includes a core power supply node configured to provide a core power supply; backup regulator configured to provide a backup power supply; memory configured to be powered by the core power supply or the backup power supply; threshold detection circuitry configured to provide a first indicator that when asserted indicates the core power supply has fallen to a first threshold, a second indicator that when asserted indicates the core power supply has fallen to a second threshold, and a third indicator that when asserted indicates the core power supply has fallen to a third threshold. The memory system also includes power sequence detection circuitry is configured to determine, upon the core power supply falling and based on which of the first, second, and third indicators are asserted, whether the asserted indicators have been asserted in a correct sequence and provide a first test result accordingly.
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