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公开(公告)号：US11848553B2
公开(公告)日：2023-12-19
申请号：US17454929
申请日：2021-11-15
申请人： NXP USA, Inc.
CPC分类号： H02H9/044 , H01L27/0248 , H02H9/04 , H02H9/046 , H01L27/02
摘要： An integrated electro-static discharge (ESD) device has a set of metal layers. Each metal layer in the set has one or more first-terminal metal features interleaved with one or more second-terminal metal features in a lateral direction, and at least one first-terminal metal feature in a metal layer of the set overlaps in a normal direction at least one second-terminal metal feature in an adjacent metal layer of the set. By overlapping metal features in the normal direction, capacitance can be added to the ESD device, which improves its operating characteristics, without increasing the layout size of the ESD device.
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公开(公告)号：US20220173136A1
公开(公告)日：2022-06-02
申请号：US17504721
申请日：2021-10-19
申请人： NXP USA, Inc.
IPC分类号： H01L27/13
摘要： There is disclosed herein an SOI IC comprising an integrated capacitor comprising a parallel arrangement of a metal-insulator-metal, MIM, capacitor, a second capacitor, a third capacitor, and a fourth capacitor:
wherein the second capacitor comprises as plates the substrate and a one of a plurality of semiconductor layers having an n-type doping, and comprises the buried oxide layer as dielectric; the third capacitor comprises as plates the polysilicon layer and a further one of a plurality of semiconductor layers having an n-type doping, and comprises an insulating layer between the plurality of semiconductor layers and the metallisation stack as dielectric; and the fourth capacitor comprises as plates the polysilicon plug and at least one of the plurality of semiconductor layers and comprises the oxide-lining as dielectric, wherein the oxide lining and the polysilicon plug form part of a lateral isolation (DTI) structure.-
公开(公告)号：US12085423B2
公开(公告)日：2024-09-10
申请号：US17313554
申请日：2021-05-06
申请人： NXP USA, Inc.
CPC分类号： G01D5/24 , G01L9/125 , G01R27/2605
摘要： A sensor interface circuit includes a continuous-time capacitance-to-voltage (C/V) converter having C/V input and output ends, the C/V input end being configured for electrical connection with first and second sense nodes of a capacitive sensor. A filter circuit is electrically coupled to the C/V output ends. The filter circuit has first and second resistors at corresponding first and second filter input ends of the filter circuit, a capacitor connected between first and second filter output ends of the filter circuit, and a chopper circuit interposed between the first and second filter input ends and the first and second filter output ends. A buffer circuit is electrically coupled with the first and second filter output ends of the filter circuit. The filter circuit applies low pass filtering of sense signals from the capacitive sensor before sampling and demodulation operations to reduce high-frequency interference in the sense signals.
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公开(公告)号：US20230253964A1
公开(公告)日：2023-08-10
申请号：US18160605
申请日：2023-01-27
申请人： NXP USA, INC.
IPC分类号： H03K19/003
CPC分类号： H03K19/00315
摘要： A circuit is disclosed, comprising: an inverter comprising first and second inverter transistors, each having: a gate terminal connected in common to a drive node, a source terminal, connected to respective first and second voltage rails, and a drain terminal connected to a common first resistor, wherein an inverter output node is connected between the first resistor and the drain terminal of a shorting one of the transistors; a tying transistor connected between the drive node and the voltage rails to which the shorting transistor is connected; a biassing circuit connected to the tying transistor's control terminal and configured to be controlled by a local drive signal and bias the tying transistor control terminal to a voltage such that the tying transistor ties the drive node of the relevant voltage rail in response to the drive signal having a first state; and a circuit for providing the local drive signal.
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公开(公告)号：US11640964B2
公开(公告)日：2023-05-02
申请号：US17504721
申请日：2021-10-19
申请人： NXP USA, Inc.
摘要： There is disclosed herein an SOI IC comprising an integrated capacitor comprising a parallel arrangement of a metal-insulator-metal, MIM, capacitor, a second capacitor, a third capacitor, and a fourth capacitor:
wherein the second capacitor comprises as plates the substrate and a one of a plurality of semiconductor layers having an n-type doping, and comprises the buried oxide layer as dielectric;
the third capacitor comprises as plates the polysilicon layer and a further one of a plurality of semiconductor layers having an n-type doping, and comprises an insulating layer between the plurality of semiconductor layers and the metallisation stack as dielectric; and the fourth capacitor comprises as plates the polysilicon plug and at least one of the plurality of semiconductor layers and comprises the oxide-lining as dielectric, wherein the oxide lining and the polysilicon plug form part of a lateral isolation (DTI) structure.-
6.发明申请公开(公告)号：US20190033903A1
公开(公告)日：2019-01-31
申请号：US15890725
申请日：2018-02-07
申请人： NXP USA, Inc.
摘要： A current regulator circuit to improve electromagnetic compatibility performance operation of an IC device includes an input to receive a regulated voltage signal, an output to provide an output voltage at a desired voltage level, the output voltage exhibiting noise from a load, a first field effect transistor FET including a first source electrode coupled to the input, a first drain electrode coupled to the output, and a first gate electrode, a voltage clamp circuit coupled to the output, the voltage clamp circuit configured to conduct a varying current based upon the noise, a constant current source to provide a constant current, and a second FET including a second source electrode coupled to the output, a second drain electrode coupled to the constant current source and to the first gate electrode, and a second gate electrode coupled to the voltage clamp circuit to mirror the varying current in the second FET.
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公开(公告)号：US12132480B2
公开(公告)日：2024-10-29
申请号：US18160605
申请日：2023-01-27
申请人： NXP USA, INC.
IPC分类号： H03K19/003
CPC分类号： H03K19/00315
摘要： A circuit is disclosed, comprising: an inverter comprising first and second inverter transistors, each having: a gate terminal connected in common to a drive node, a source terminal, connected to respective first and second voltage rails, and a drain terminal connected to a common first resistor, wherein an inverter output node is connected between the first resistor and the drain terminal of a shorting one of the transistors; a tying transistor connected between the drive node and the voltage rails to which the shorting transistor is connected; a biasing circuit connected to the tying transistor's control terminal and configured to be controlled by a local drive signal and bias the tying transistor control terminal to a voltage such that the tying transistor ties the drive node of the relevant voltage rail in response to the drive signal having a first state; and a circuit for providing the local drive signal.
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公开(公告)号：US11057073B2
公开(公告)日：2021-07-06
申请号：US16879280
申请日：2020-05-20
申请人： NXP USA, Inc.
摘要： An integrated circuit for use in a differential network bus node comprising: a transceiver having a first transceiver input-output terminal and a second transceiver input-output terminal; a physical layer high terminal connected to the first transceiver input-output-terminal; a physical layer low terminal connected to the second transceiver input-output terminal; and a physical layer interface circuit comprising: a first low frequency RC matching circuit and a first high frequency RC matching circuit each connected between the first transceiver input-output-terminal and a first reference terminal; and a second low frequency RC matching circuit and a second high frequency RC matching circuit each connected between the second transceiver input-output terminal and a second reference terminal.
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公开(公告)号：US20200373959A1
公开(公告)日：2020-11-26
申请号：US16879280
申请日：2020-05-20
申请人： NXP USA, Inc.
摘要： An integrated circuit (202) for use in a differential network bus node (200) comprising: a transceiver (212) having a first transceiver input-output terminal (214) and a second transceiver input-output terminal (216); a physical layer high terminal (208) connected to the first transceiver input-output-terminal (214); a physical layer low terminal (210) connected to the second transceiver input-output terminal (216); and a physical layer interface circuit (234) comprising: a first low frequency RC matching circuit (236) and a first high frequency RC matching circuit (240) each connected between the first transceiver input-output-terminal (214) and a first reference terminal (238); and a second low frequency RC matching circuit (242) and a second high frequency RC matching circuit (246) each connected between the second transceiver input-output terminal (216) and a second reference terminal (244).
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10.发明申请公开(公告)号：US20200220626A1
公开(公告)日：2020-07-09
申请号：US16284469
申请日：2019-02-25
申请人： NXP USA, INC.
摘要： An example apparatus that employs circuitry operating in response to digital clock signal circuitry. The apparatus includes first circuitry and second circuitry. The first circuitry produces a high-frequency digital clock signal characterized by a high frequency which carries radiative noise interference and by a modulated low-frequency digital clock signal characterized by a low frequency modulated by a first type of modulation. The second circuitry produces another low-frequency digital clock signal by combining a disparate modulation signal and a feedback signal derived from the other low-frequency digital clock signal, wherein the disparate modulation signal is characterized by modulating the feedback signal via a second type of modulation that is independent of the first type of modulation and by cancellation/blocking of the radiative noise interference manifested by the circuitry operating in response to the digital clock signal circuitry.
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