公开(公告)号：US20190005396A1

公开(公告)日：2019-01-03

申请号：US15878888

申请日：2018-01-24

申请人： NXP USA, Inc.

发明人： Robert Krutsch ,  Michael Staudenmaier ,  Stephan Herrmann

IPC分类号： G06N5/04 ,  G06F17/30 ,  G05D1/00 ,  G06N99/00

CPC分类号： G06N5/045 ,  G05D1/0088 ,  G06F16/285 ,  G06F16/9017 ,  G06K9/00805 ,  G06K9/00986 ,  G06K9/6282 ,  G06N20/00

摘要： A processing engine for classifying data according to a decision tree having n-nodes is disclosed, wherein each node is represented by a respective test according to which a flag may be set or unset, comprising: a respective test unit and corresponding to each node, having an output flag and being configured to set or unset the respective output flag according to an output of the respective test; a memory configured to hold an n-bit word, each bit corresponding to a one of the respective output flags; and a data-structure configured as a look up table, each entry of the look up table representing a class of the data. Corresponding methods are also disclosed, as are devices and systems incorporating such processing engines.

公开(公告)号：US20180157848A1

公开(公告)日：2018-06-07

申请号：US15701517

申请日：2017-09-12

申请人： NXP USA, Inc.

发明人： Joachim Fader ,  Robert Krutsch ,  Dirk Wendel

IPC分类号： G06F21/60 ,  G06F11/08 ,  G06F11/07 ,  G06F13/16

CPC分类号： G06F21/602 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/08 ,  G06F11/1048 ,  G06F11/1052 ,  G06F13/1668

摘要： A system on a chip (SoC) and method of operation are described. A data processor has a processor data word size of p×octets and is configured to handle data items having a data item size which is a non-integer multiple of the processor data word size. A memory controller is configured to write or read data items to a memory as multiples of m×octets. Data can be sent between the data processor and the memory controller on a bus. A data protection code generator is configured to generate a data protection code for a data item generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller which writes at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address. A data protection code checker is configured to receive a read data protection code and a read data item and to check the read data item for an error using the read data protection code. The memory controller reads at least one octet including at least a portion of the read data item and at least a portion of the read data protection code from a read address.

公开(公告)号：US10726345B2

公开(公告)日：2020-07-28

申请号：US15878888

申请日：2018-01-24

申请人： NXP USA, Inc.

发明人： Robert Krutsch ,  Michael Staudenmaier ,  Stephan Herrmann

IPC分类号： G06N5/04 ,  G06K9/62 ,  G06K9/00 ,  G06N20/00 ,  G06F16/90 ,  G05D1/08 ,  G06F16/28 ,  G06F16/901 ,  G05D1/00

摘要： A processing engine for classifying data according to a decision tree having n-nodes is disclosed, wherein each node is represented by a respective test according to which a flag may be set or unset, comprising: a respective test unit and corresponding to each node, having an output flag and being configured to set or unset the respective output flag according to an output of the respective test; a memory configured to hold an n-bit word, each bit corresponding to a one of the respective output flags; and a data-structure configured as a look up table, each entry of the look up table representing a class of the data. Corresponding methods are also disclosed, as are devices and systems incorporating such processing engines.

公开(公告)号：US10318466B2

公开(公告)日：2019-06-11

申请号：US15628334

申请日：2017-06-20

申请人： NXP USA, Inc.

发明人： Robert Krutsch ,  Christian Tuschen

IPC分类号： G06F11/07 ,  G06F13/42 ,  G06F13/36 ,  G06F13/40 ,  G06F15/76 ,  G06F13/38

摘要： A method and apparatus for handling outstanding interconnect transactions between a master device and an interconnect component. For example, a transaction intervention module coupled to an interconnect component and a master device of the interconnect component. The transaction intervention module is arranged to receive an indication of a functional state of the master device. If the master device is indicated as being in a faulty functional state the transaction intervention module is further arranged to determine whether any interconnect transactions initiated by the master device with the interconnect component are outstanding. If it is determined that at least one interconnect transaction initiated by the master device is outstanding, the transaction intervention module is arranged to finalize the at least one outstanding interconnect transaction with the interconnect component.

公开(公告)号：US10311241B2

公开(公告)日：2019-06-04

申请号：US15701517

申请日：2017-09-12

申请人： NXP USA, Inc.

发明人： Joachim Fader ,  Robert Krutsch ,  Dirk Wendel

IPC分类号： G06F11/30 ,  G06F21/60 ,  G06F11/08 ,  G06F13/16 ,  G06F11/07 ,  G06F11/10

摘要： A system on a chip (SoC) and method of operation are described. A data processor has a processor data word size of p×octets and is configured to handle data items having a data item size which is a non-integer multiple of the processor data word size. A memory controller is configured to write or read data items to a memory as multiples of m×octets. Data can be sent between the data processor and the memory controller on a bus. A data protection code generator is configured to generate a data protection code for a data item generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller which writes at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address. A data protection code checker is configured to receive a read data protection code and a read data item and to check the read data item for an error using the read data protection code. The memory controller reads at least one octet including at least a portion of the read data item and at least a portion of the read data protection code from a read address.