公开(公告)号：US08645897B1

公开(公告)日：2014-02-04

申请号：US13735054

申请日：2013-01-07

Applicant: Nandini ,  Gaurav Gupta ,  Rohit Srivastava

Inventor： Nandini ,  Gaurav Gupta ,  Rohit Srivastava

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/66

Abstract: An integrated circuit (IC) design verification system includes a memory for storing an IC design and a processor in communication with the memory. The IC design includes multiple IP cores and the design verification apparatus includes multiple verification modules. The processor configures a first set of connections between the IP cores and the verification modules based on a first connection database and verifies each IP core independently using the first set of connections. Thereafter, the processor configures a second set of connections between the IP cores and the verification modules based on a second connection database generated based on the first connection database, and verifies the multiple IP cores together using the second set of connections.

Abstract translation: 集成电路（IC）设计验证系统包括用于存储IC设计的存储器和与存储器通信的处理器。 IC设计包括多个IP核，设计验证装置包括多个验证模块。 处理器基于第一连接数据库配置IP核和验证模块之间的第一组连接，并使用第一组连接独立地验证每个IP核。 此后，处理器基于基于第一连接数据库生成的第二连接数据库来配置IP核和验证模块之间的第二组连接，并且使用第二组连接来验证多个IP内核。

公开(公告)号：US20160070846A1

公开(公告)日：2016-03-10

申请号：US14481899

申请日：2014-09-09

Applicant: Nandini ,  Rohit Srivastava

Inventor： Nandini ,  Rohit Srivastava

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5022

Abstract: A method for testing an integrated circuit design exercises the design using a set of simulation signals, and partitions a representation of the design into a first set of active elements and a second set of inactive elements. Only the active elements of the first set are exercised using a second set of simulation signals during verification of the integrated circuit design.

Abstract translation: 用于测试集成电路设计的方法使用一组模拟信号来执行设计，并将设计的表示分割成第一组有源元件和第二组非活动元件。 在验证集成电路设计期间，仅使用第二组模拟信号来执行第一组的有源元件。