公开(公告)号：US09406765B1

公开(公告)日：2016-08-02

申请号：US14811849

申请日：2015-07-29

Applicant: Nano and Advanced Materials Institute Limited

Inventor： Caiming Sun ,  Chun Zhao ,  Ka Chon Wong

IPC: H01L29/51 ,  H01L29/00 ,  H01L27/11 ,  H01L29/423 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L29/513 ,  G11C2216/06 ,  H01L21/28273 ,  H01L29/0665 ,  H01L29/42332

Abstract: Si/SiO2 core/shell nanostructures with sizes below 30 nm as trapping points in UV curable hybrid organic-inorganic gate dielectrics are presented in order to investigate printable nano floating gate transistors. Not only does the novelty of this invention comes from fabricating high-quality hybrid organic/inorganic gate dielectric layer by Sol-Gel process at low temperature but also incorporating the monolayer of high-density of Si nanoparticles (NPs) without obvious interface defects and keeping the quality of dielectric layers. Fixed-charge trapping defects are successfully removed from hybrid dielectrics by UV curing together with low temperature thermal curing and mobile charges solely related to Si/SiO2 core/shell nanostructures on charge trapping layer clearly demonstrate memory effects on printable device. Thin/uniform SiO2 shell on each Si NP functions as tunneling layer of flash memory devices, significantly simplifying the fabrication of printable nano floating gate memory device.

Abstract translation: 提出了尺寸低于30nm的Si / SiO 2核/壳纳米结构作为紫外线固化混合有机 - 无机栅极电介质中的捕集点，以便研究可印刷的纳米浮栅晶体管。 本发明的新颖性不仅在于通过溶胶 - 凝胶法在低温下制造高质量的混合有机/无机栅介电层，而且还掺入高密度的Si纳米颗粒（NP）的单层，而没有明显的界面缺陷和保持 电介质层的质量。 固定电荷捕获缺陷通过UV固化与低温热固化以及仅与电荷捕获层上的Si / SiO 2核/壳纳米结构相关的移动电荷成功地从混合电介质中去除，清楚地显示了对可印刷器件的记忆效应。 每个Si NP上的薄/均匀的SiO 2壳体用作闪存器件的隧道层，显着简化了可印刷的纳米浮动栅极存储器件的制造。