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    METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVCIE HAVING CAPACITOR ELEMENT
    1.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVCIE HAVING CAPACITOR ELEMENT 审中-公开
    具有电容元件的半导体集成电路制造方法

    公开(公告)号：US20110012181A1

    公开(公告)日：2011-01-20

    申请号：US12890431

    申请日：2010-09-24

    申请人： Naotaka HASHIMOTO ,  Yutaka Hoshino ,  Shuji Ikeda

    发明人： Naotaka HASHIMOTO ,  Yutaka Hoshino ,  Shuji Ikeda

    IPC分类号： H01L27/108 ,  H01L27/092 ,  H01L21/8238

    CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

    摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

    摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

    Process for manufacturing semiconductor integrated circuit device
    3.
    发明授权
    Process for manufacturing semiconductor integrated circuit device 有权
    半导体集成电路器件制造工艺

    公开(公告)号：US06245611B1

    公开(公告)日：2001-06-12

    申请号：US09434385

    申请日：1999-11-05

    申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

    发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

    IPC分类号： H01L218244

    CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

    摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

    摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

    METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING CAPACITOR ELEMENT
    4.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING CAPACITOR ELEMENT 失效
    制造具有电容元件的半导体集成电路器件的制造方法

    公开(公告)号：US20080061381A1

    公开(公告)日：2008-03-13

    申请号：US11926321

    申请日：2007-10-29

    申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

    发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

    IPC分类号： H01L27/108 ,  H01L21/8244

    CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

    摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

    摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

    Method of manufacturing semiconductor integrated circuit device having capacitor element
    6.
    发明申请
    Method of manufacturing semiconductor integrated circuit device having capacitor element 失效
    具有电容元件的半导体集成电路器件的制造方法

    公开(公告)号：US20050042827A1

    公开(公告)日：2005-02-24

    申请号：US10951940

    申请日：2004-09-29

    申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

    发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

    IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/10 ,  H01L27/11 ,  H01L21/336

    CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

    摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

    摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

    Process for manufacturing semiconductor integrated circuit device
    8.
    发明授权
    Process for manufacturing semiconductor integrated circuit device 失效
    半导体集成电路器件制造工艺

    公开(公告)号：US6030865A

    公开(公告)日：2000-02-29

    申请号：US66763

    申请日：1998-04-28

    申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

    发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

    IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/10 ,  H01L27/11

    CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/1104 ,  H01L27/1112 ,  H01L27/0207 ,  H01L2924/0002 ,  Y10S257/903

    摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

    摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

    METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING CAPACITOR ELEMENT
    9.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING CAPACITOR ELEMENT 审中-公开
    制造具有电容元件的半导体集成电路器件的制造方法

    公开(公告)号：US20100001329A1

    公开(公告)日：2010-01-07

    申请号：US12559274

    申请日：2009-09-14

    申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

    发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

    IPC分类号： H01L27/11 ,  H01L27/108

    CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

    摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

    摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

    Method of manufacturing semiconductor integrated circuit device having capacitor element
    10.
    发明授权
    Method of manufacturing semiconductor integrated circuit device having capacitor element 有权
    具有电容器元件的半导体集成电路器件的制造方法

    公开(公告)号：US07199433B2

    公开(公告)日：2007-04-03

    申请号：US10756305

    申请日：2004-01-14

    申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

    发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

    IPC分类号： H01L27/108

    CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

    摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

    摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。