公开(公告)号：US20080151080A1

公开(公告)日：2008-06-26

申请号：US11963178

申请日：2007-12-21

申请人： Naoto Osaka ,  Hisao Kunitani ,  Tatuo Itoman

发明人： Naoto Osaka ,  Hisao Kunitani ,  Tatuo Itoman

IPC分类号： H04N5/217

CPC分类号： G06T5/002 ,  G06T2207/10016 ,  G06T2207/20012 ,  G06T2207/20192

摘要： A noise shaping processing part performs noise shaping processing on pixel data. An adding circuit performs accumulative adding processing on the noise-shaped pixel data. A first bit-shift part performs bit-shift processing on the accumulatively-added and noise-shaped pixel data. A second bit-shift part performs bit-shift processing on unprocessed pixel data. An inter-pixel subtracting circuit calculates a gradation level difference between neighboring current pixel and previous pixel in a horizontal direction in the unprocessed pixel data. A boundary judging circuit judges presence of a boundary between a low-gradation area and a high-gradation area in the horizontal direction of the unprocessed pixel data, based on a comparison between the gradation level difference and a prescribed threshold value. A selecting circuit selects an output of the first bit-shift part when the boundary judging circuit judges there is no boundary, and selects an output of the second bit-shift part when judged there is a boundary.

摘要翻译： 噪声整形处理部对像素数据进行噪声整形处理。 加法电路对噪声形状的像素数据进行累加处理。 第一位移部分对累加和噪声形状的像素数据进行位移处理。 第二位移部件对未处理的像素数据执行位移处理。 像素间减法电路计算未处理像素数据中的相邻的当前像素与水平方向上的前一像素之间的灰度级差。 边界判断电路基于灰度级差与规定的阈值之间的比较来判断未处理像素数据的水平方向上的低灰度区域和高灰度区域之间的边界的存在。 当边界判断电路判断没有边界时，选择电路选择第一位移部分的输出，并且当判断有边界时选择第二位移部分的输出。

公开(公告)号：US20070229482A1

公开(公告)日：2007-10-04

申请号：US11730831

申请日：2007-04-04

申请人： Hiroyuki Morinaga ,  Hiroyuki Kageyama ,  Tsutomu Sakakibara ,  Tatuo Itoman ,  Naoto Osaka

发明人： Hiroyuki Morinaga ,  Hiroyuki Kageyama ,  Tsutomu Sakakibara ,  Tatuo Itoman ,  Naoto Osaka

IPC分类号： G09G5/00

CPC分类号： G09G5/006 ,  G09G5/393 ,  G09G2320/10 ,  G09G2340/0435 ,  G09G2360/18

摘要： A memory access switchover circuit relays a data access to the image memory by a writing control circuit and a data access to the image memory by the display control circuit. A blanking period change control circuit extends the blanking period in a display frame at timing of reception of start of the writing operation upon receiving the start of the writing operation to the image memory by the wiring control circuit. The writing control circuit outputs a request for writing the image data to the memory access switchover circuit upon receiving the input of the image data. The memory access switchover circuit switches from the data access by the display control circuit to the data access by the writing control circuit when the request for writing is received.

摘要翻译： 存储器存取切换电路通过写入控制电路中继对图像存储器的数据访问，以及通过显示控制电路对图像存储器的数据访问。 消隐周期变化控制电路在接收到通过布线控制电路向图像存储器的写入操作的开始的接收开始写入操作的定时时，在显示帧中延长消隐周期。 写入控制电路在接收到图像数据的输入时输出将图像数据写入存储器存取切换电路的请求。 当接收到写入请求时，存储器访问切换电路从显示控制电路的数据访问切换到写入控制电路的数据访问。

公开(公告)号：US07271808B2

公开(公告)日：2007-09-18

申请号：US10833287

申请日：2004-04-28

申请人： Seiichi Moriyama ,  Naoto Osaka ,  Takashi Koizumi ,  Hiroyuki Kageyama ,  Hiroyuki Morinaga ,  Noriko Kaku ,  Yumiko Kataoka

发明人： Seiichi Moriyama ,  Naoto Osaka ,  Takashi Koizumi ,  Hiroyuki Kageyama ,  Hiroyuki Morinaga ,  Noriko Kaku ,  Yumiko Kataoka

IPC分类号： G06F12/02 ,  G06F15/167 ,  G09G3/36

CPC分类号： G09G5/001 ,  G06F3/147 ,  G09G3/3611

摘要： When a contention is detected between a memory write address and a display read address in a memory circuit which stores display data, a host retry pulse generating circuit generates a display read signal and a display line data transfer signal based on a memory write clock, and supplies these to the memory circuit while supplying the display line data transfer signal to a line latch circuit. Alternatively, upon detection of the contention above, a same line re-display read processing circuit performs same line re-display read processing without moving to the next line, and supplies a display read signal and a display line data transfer signal to the memory circuit while supplying the display line data transfer signal to the line latch circuit.

摘要翻译： 当在存储显示数据的存储器电路中的存储器写入地址和显示器读取地址之间检测到争用时，主机重试脉冲发生电路基于存储器写入时钟产生显示读取信号和显示行数据传送信号，以及 将显示行数据传送信号提供给线锁存电路，将其提供给存储电路。 或者，在检测到上述争用时，同一行重新显示读取处理电路在不移动到下一行的情况下执行相同的行重新显示读取处理，并将显示读取信号和显示行数据传送信号提供给存储器电路 同时向线路锁存电路提供显示线数据传送信号。