公开(公告)号：US06650637B1

公开(公告)日：2003-11-18

申请号：US09211497

申请日：1998-12-14

申请人： Narendra K. Bansal ,  Kenneth A. Becker ,  James S. Lavranchuk

发明人： Narendra K. Bansal ,  Kenneth A. Becker ,  James S. Lavranchuk

IPC分类号： H04L1250

CPC分类号： H04L49/103 ,  H04Q11/0478

摘要： A high capacity digital non-blocking cross-connect switching fabric is realized by employing a multi-port RAM based space-time switch having a plurality of write circuits and a plurality of read circuits, each of which operates at a timing rate that is a prescribed fraction of the input/output clock rate of the input/output ports of the multi-port RAM based cross-connect switching fabric. The at least one multi-port RAM switch unit has a plurality of write circuits and a plurality of read circuits, each of which operates at a timing rate that is a prescribed fraction of the input/output clock rate of the input/output ports of the multi-port RAM based cross-connect switching fabric. Additionally, in one embodiment, each of the write circuits and each of the read circuits has independent and unrestricted access to all data storage positions in each of a plurality of storage units that make up the at least one multi-port RAM switch unit. Because the write circuits and each of the read circuits are operating at the prescribed fraction of the multi-port RAM switch unit input/output clock rate, a multi-port RAM based cross-connect switching fabric is realizable which has a significantly larger storage capacity that is accessible within a reasonable access time. In one embodiment of the invention, a plurality of multi-port RAM switch units is employed to realize a multi-port RAM based non-blocking cross-connect switching fabric. In a specific embodiment, the fractional write rate is exploited so that a plurality of input ports can be served by a single write circuit. In another embodiment, each write circuit is assigned exclusive access to a particular segment of the write address space that is different from that assigned to any other write circuit. Furthermore, since the read circuits are operating at a fraction of the output port clock rate, each of the read circuits can serve a plurality of output ports by delivering read signal elements from the multi-port RAM switch unit to the output ports in a round robin fashion. Additionally, in another embodiment of the invention, each read circuit is assigned exclusive access to a particular segment of the read address space that is different from that assigned to any other read circuit. Consequently, the capacity of the multi-port RAM based cross-connect switching fabric is markedly increased.

公开(公告)号：US5285441A

公开(公告)日：1994-02-08

申请号：US852604

申请日：1992-03-17

申请人： Narendra K. Bansal ,  Sid Chaudhuri ,  Shahrukh S. Merchant ,  Donald J. Wemple

发明人： Narendra K. Bansal ,  Sid Chaudhuri ,  Shahrukh S. Merchant ,  Donald J. Wemple

IPC分类号： H04L1/22 ,  H04L1/06 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L49/153 ,  H04L1/06 ,  H04Q11/0478 ,  H04L2012/561 ,  H04L2012/5627

摘要： An errorless line protection apparatus involves receipt of data from an active line and a standby line. A determination is made as to whether the data from the active line leads or lags the data on the standby line. A switching system directs the leading data to a lead channel containing a controllable amount of time delay up to the maximum amount that the leading data is expected to led the lagging data. Lagging data is directed to a lag channel. A selected one of the data from the lead channel or the lag channel is delivered to an output line.

摘要翻译： 无误线路保护装置涉及从有效线路和备用线路接收数据。 确定来自活动线的数据是否导致或滞留备用线路上的数据。 交换系统将领先数据引导到包含可控量的时间延迟的引导通道，直到引导数据预期导致滞后数据的最大量。 滞后数据被引导到滞后通道。 来自引导通道或滞后通道的选择的一个数据被传送到输出线。

公开(公告)号：US07304988B2

公开(公告)日：2007-12-04

申请号：US10402916

申请日：2003-03-28

申请人： Narendra K. Bansal

发明人： Narendra K. Bansal

IPC分类号： H04L12/52 ,  H04Q11/04

CPC分类号： H04Q11/0421 ,  H04Q2213/13076 ,  H04Q2213/13292 ,  H04Q2213/1332

摘要： A digital cross-connect switching system that has a single-stage architecture, a scalable bandwidth, and reduced connection memory storage requirements. The scalable bandwidth digital cross-connect switching system includes a plurality of digital cross-connect building blocks. Each digital cross-connect building block includes at least one cross-connect having a plurality of input ports and a plurality of output ports, at least one connection memory communicatively coupled to the cross-connect, and at least one OR gate. Bandwidth is scaled in the digital cross-connect switching system by interconnecting predetermined numbers of the digital cross-connect building blocks. In general, the size of the digital cross-connect switching system increases as the square of the bandwidth requirement.

摘要翻译： 具有单级架构，可扩展带宽和减少的连接存储器存储要求的数字交叉连接交换系统。 可扩展带宽数字交叉连接交换系统包括多个数字交叉连接构建块。 每个数字交叉连接构建块包括具有多个输入端口和多个输出端口的至少一个交叉连接器，至少一个通信地耦合到交叉连接的连接存储器以及至少一个或门。 通过互连预定数量的数字交叉连接构建块，数字交叉连接交换系统中的带宽被缩放。 一般来说，数字交叉连接交换系统的大小随着带宽要求的平方而增加。

公开(公告)号：US07212523B2

公开(公告)日：2007-05-01

申请号：US10401282

申请日：2003-03-27

申请人： Narendra K. Bansal ,  Gary Martin

发明人： Narendra K. Bansal ,  Gary Martin

IPC分类号： H04L12/50

CPC分类号： H04Q11/0421 ,  H04Q3/68 ,  H04Q2213/13076 ,  H04Q2213/13292 ,  H04Q2213/13299 ,  H04Q2213/1332 ,  H04Q2213/1334 ,  H04Q2213/13341

摘要： An architecture for a high bandwidth digital cross-connect switching system that is internally non-blocking, has a simpler layout, and employs a reduced number of logic gates. The high bandwidth digital cross-connect switching architecture comprises a Time Division Multiplexing (TDM) cross-connect including M space/time switches. Each space/time switch includes an input bus, an output bus, N×W Flip-Flops (FFs) for storing input data, W N-by-N switches for sorting the data according to predetermined cross-connection requirements, and N×W FFs for storing output data, in which “N” corresponds to the number of input ports and the number of output ports in the N-by-N switch, and “W” corresponds to the width of each data word. Each N-by-N switch includes N×W N-to-1 selectors, and the M space/time switches include N×W M-to-1 selectors, thereby allowing an effective N×M-to-1 selection to be performed on the data words.

摘要翻译： 用于内部非阻塞的高带宽数字交叉连接交换系统的架构具有更简单的布局，并且采用减少数量的逻辑门。 高带宽数字交叉连接交换架构包括包括M个空间/时间交换机的时分复用（TDM）交叉连接。 每个空间/时间开关包括输入总线，输出总线，用于存储输入数据的NxW触发器（FF），用于根据预定的交叉连接要求对数据进行排序的N N个N开关，以及用于存储的NxWFF 输出数据，其中“N”对应于N-N开关中的输入端口数量和输出端口数量，“W”对应于每个数据字的宽度。 每个N-N开关包括N×W个N-1选择器，并且M个空间/时间开关包括N×W M-1选择器，从而允许对数据字进行有效的N×M-1选择。