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    Techniques for rate governing of a display data stream
    1.
    发明授权
    Techniques for rate governing of a display data stream 有权
    技术用于显示数据流的速率控制

    公开(公告)号：US09304731B2

    公开(公告)日：2016-04-05

    申请号：US13997237

    申请日：2011-12-21

    申请人： Nausheen Ansari ,  Todd M. Witter

    发明人： Nausheen Ansari ,  Todd M. Witter

    IPC分类号： G06F3/00 ,  G06F3/14 ,  G09G5/00 ,  G06F3/03 ,  H04L29/06 ,  H04N17/04 ,  H04L12/801 ,  G06F13/38 ,  H04L12/835 ,  G09G5/36

    CPC分类号： G06F3/1423 ,  G06F3/03 ,  G06F13/385 ,  G09G5/00 ,  G09G5/006 ,  G09G5/363 ,  G09G2354/00 ,  G09G2370/10 ,  G09G2370/20 ,  H04L29/06 ,  H04L47/10 ,  H04L47/30 ,  H04N17/04

    摘要： Techniques for rate governing of a display data stream are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics management module comprising a differential analyzer. In some embodiments, the graphics management module may be operative on the processor circuit to determine a target display data transmission rate for one or more displays, determine, by the differential analyzer, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate, transmit the one or more display data packets based on the actual display data transmission rate, and accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets. Other embodiments are described and claimed.

    摘要翻译： 描述了显示数据流的速率控制技术。 在一个实施例中，例如，装置可以包括处理器电路和包括差分分析器的图形管理模块。 在一些实施例中，图形管理模块可以在处理器电路上操作以确定一个或多个显示器的目标显示数据传输速率，由差分分析器确定基于一个或多个显示数据分组的实际显示数据传输速率 根据目标显示数据传输速率，基于实际的显示数据传输速率发送一个或多个显示数据分组，并且累积一个或多个显示数据的实际显示数据传输速率与目标显示数据传输速率之间的差异 数据包 描述和要求保护其他实施例。

    TECHNIQUES FOR RATE GOVERNING OF A DISPLAY DATA STREAM
    2.
    发明申请
    TECHNIQUES FOR RATE GOVERNING OF A DISPLAY DATA STREAM 有权
    显示数据流的速率控制技术

    公开(公告)号：US20140297902A1

    公开(公告)日：2014-10-02

    申请号：US13997237

    申请日：2011-12-21

    申请人： Nausheen Ansari ,  Todd M. Witter

    发明人： Nausheen Ansari ,  Todd M. Witter

    IPC分类号： G09G5/00 ,  G06F3/14

    CPC分类号： G06F3/1423 ,  G06F3/03 ,  G06F13/385 ,  G09G5/00 ,  G09G5/006 ,  G09G5/363 ,  G09G2354/00 ,  G09G2370/10 ,  G09G2370/20 ,  H04L29/06 ,  H04L47/10 ,  H04L47/30 ,  H04N17/04

    摘要： Techniques for rate governing of a display data stream are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics management module comprising a differential analyzer. In some embodiments, the graphics management module may be operative on the processor circuit to determine a target display data transmission rate for one or more displays, determine, by the differential analyzer, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate, transmit the one or more display data packets based on the actual display data transmission rate, and accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets. Other embodiments are described and claimed.

    摘要翻译： 描述了显示数据流的速率控制技术。 在一个实施例中，例如，装置可以包括处理器电路和包括差分分析器的图形管理模块。 在一些实施例中，图形管理模块可以在处理器电路上操作以确定一个或多个显示器的目标显示数据传输速率，由差分分析器确定基于一个或多个显示数据分组的实际显示数据传输速率 根据目标显示数据传输速率，基于实际的显示数据传输速率发送一个或多个显示数据分组，并且累积一个或多个显示数据的实际显示数据传输速率与目标显示数据传输速率之间的差异 数据包 描述和要求保护其他实施例。

    Link Bandwidth Improvement Techniques
    3.
    发明申请
    Link Bandwidth Improvement Techniques 审中-公开

    公开(公告)号：US20190268629A1

    公开(公告)日：2019-08-29

    申请号：US16413410

    申请日：2019-05-15

    申请人： Nausheen Ansari ,  Ziv Kabiry

    发明人： Nausheen Ansari ,  Ziv Kabiry

    IPC分类号： H04N21/238 ,  H04N21/647 ,  H04N21/633 ,  H04N21/24

    摘要： One embodiment provides a video transport system. The video transport system includes graphics processing circuitry to generate a video transport unit (TU) corresponding to a scan line of a first video frame that is unchanged from a second video frame, wherein the video TU includes a control sequence and an unchanged data payload corresponding to a defined number of pixels of the scan line of the first video frame. The video transport system of this embodiment also includes source tunneling bridge circuitry to generate a bus TU based on the video TU; the source tunneling bridge circuitry to parse the control sequence or the unchanged data payload of the video TU, and to generate the bus TU having a header that includes a field to identify the defined number of pixels of the unchanged data payload, and to eliminate, in whole or in part, the unchanged data payload in the bus TU.

    COMBINED PANEL SELF-REFRESH (PSR) AND ADAPTIVE SYNCHRONIZATION SYSTEMS AND METHODS
    5.
    发明申请
    COMBINED PANEL SELF-REFRESH (PSR) AND ADAPTIVE SYNCHRONIZATION SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20190325844A1

    公开(公告)日：2019-10-24

    申请号：US16457723

    申请日：2019-06-28

    申请人： Nausheen Ansari ,  Gary Smith

    发明人： Nausheen Ansari ,  Gary Smith

    IPC分类号： G09G5/00

    摘要： The present disclosure is directed to systems and methods of maintaining source device to sink device synchronization in systems in which the source device enters a Panel Self-Refresh (PSR/PSR2) mode and the sink device enables adaptive synchronization with the source device. To maintain synchronization, in some instances the source device and the sink device may maintain synchronization contemporaneous with at least a portion of the PSR/PSR2 operating mode. To maintain synchronization, in some instances, a high-bandwidth communications link may be maintained between the source device and the sink device. In some instances, synchronization between the source device and the sink device may be interrupted upon the source device entering the PSR/PSR2 operating mode and may be re-established upon the source device exiting the PSR/PSR2 operating mode.

    DISPLAY SYNCHRONIZATION
    7.
    发明申请
    DISPLAY SYNCHRONIZATION 审中-公开

    公开(公告)号：US20180061303A1

    公开(公告)日：2018-03-01

    申请号：US15253359

    申请日：2016-08-31

    申请人： Nausheen Ansari ,  Gal Yedidia

    发明人： Nausheen Ansari ,  Gal Yedidia

    IPC分类号： G09G3/20

    CPC分类号： G09G3/2092 ,  G06F3/14 ,  G09G3/2018 ,  G09G5/006 ,  G09G5/008 ,  G09G5/12 ,  G09G2310/0291

    摘要： Techniques for synchronizing a display transmitter and display panel are described. An example display panel includes a timing controller to receive display data from a transmitter and render the display data on a display screen of the display panel. The display panel is in a first clock domain and the transmitter is in a second clock domain which is derived separately from the first clock domain. The display panel also includes a time code generator to generate a first display time code and a frequency adjuster to receive a second display time code from the transmitter. The frequency adjuster adjusts the clock frequency of the display panel based on the first display time code and the second display time code.