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    Systems and methods for reduced latency loop correction
    1.
    发明授权
    Systems and methods for reduced latency loop correction 有权
    用于减少等待时间循环校正的系统和方法

    公开(公告)号：US08610608B2

    公开(公告)日：2013-12-17

    申请号：US13415430

    申请日：2012-03-08

    申请人： Nayak Ratnakar Aravind ,  Scott M. Dziak ,  Haitao Xia

    发明人： Nayak Ratnakar Aravind ,  Scott M. Dziak ,  Haitao Xia

    IPC分类号： H03M1/06

    CPC分类号： H03J7/04

    摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes: a data detector circuit, a low latency detection circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output, and to provide a loop error as a difference between the detected output and the first signal. The low latency detection circuit operable to process a second signal derived from the data input to yield a fast detector output, and to provide a generated error as a difference between the fast detector output and the second signal. The error calculation circuit is operable to calculate an error value based at least in part on the generated error and the loop error.

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，讨论了包括数据检测器电路，低延迟检测电路和误差计算电路的数据处理电路。 数据检测器电路可操作以对从数据输入导出的第一信号执行数据检测处理，以产生检测到的输出，并提供循环误差作为检测到的输出与第一信号之间的差。 低延迟检测电路可操作以处理从数据输入得到的第二信号以产生快速检测器输出，并且将产生的误差提供为快速检测器输出和第二信号之间的差。 误差计算电路可操作以至少部分地基于所产生的误差和环路误差来计算误差值。

    Systems and Methods for Reduced Latency Loop Correction
    2.
    发明申请
    Systems and Methods for Reduced Latency Loop Correction 有权
    减少延迟循环校正的系统和方法

    公开(公告)号：US20130238944A1

    公开(公告)日：2013-09-12

    申请号：US13415430

    申请日：2012-03-08

    申请人： Nayak Ratnakar Aravind ,  Scott M. Dziak ,  Haitao Xia

    发明人： Nayak Ratnakar Aravind ,  Scott M. Dziak ,  Haitao Xia

    IPC分类号： G06F11/07

    CPC分类号： H03J7/04

    摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes: a data detector circuit, a low latency detection circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output, and to provide a loop error as a difference between the detected output and the first signal. The low latency detection circuit operable to process a second signal derived from the data input to yield a fast detector output, and to provide a generated error as a difference between the fast detector output and the second signal. The error calculation circuit is operable to calculate an error value based at least in part on the generated error and the loop error.

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，讨论了包括数据检测器电路，低延迟检测电路和误差计算电路的数据处理电路。 数据检测器电路可操作以对从数据输入导出的第一信号执行数据检测处理，以产生检测到的输出，并提供循环误差作为检测到的输出与第一信号之间的差。 低延迟检测电路可操作以处理从数据输入得到的第二信号以产生快速检测器输出，并且将产生的误差提供为快速检测器输出和第二信号之间的差。 误差计算电路可操作以至少部分地基于所产生的误差和环路误差来计算误差值。

    Systems and Methods for Digital MRA Compensation
    3.
    发明申请
    Systems and Methods for Digital MRA Compensation 有权
    数字MRA补偿系统与方法

    公开(公告)号：US20130198421A1

    公开(公告)日：2013-08-01

    申请号：US13362466

    申请日：2012-01-31

    申请人： Nayak Ratnakar Aravind ,  Yu Liao ,  Haitao Xia

    发明人： Nayak Ratnakar Aravind ,  Yu Liao ,  Haitao Xia

    IPC分类号： G06F13/12

    CPC分类号： H03M1/12 ,  G06F13/385

    摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an analog to digital converter circuit, and a magneto-resistive adjustment circuit. The analog to digital converter circuit is operable to convert an input signal into corresponding digital samples. The magneto-resistive adjustment circuit is operable to reduce signal asymmetry in the digital samples due to sensing by a magneto-resistive head to yield a corrected output.

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，讨论了包括：模数转换器电路和磁阻调节电路的数据处理系统。 模数转换器电路可操作以将输入信号转换成对应的数字采样。 磁阻调节电路可操作以由于由磁阻头感测而产生校正输出，从而减少数字采样中的信号不对称性。

    Systems and methods for digital MRA compensation
    4.
    发明授权
    Systems and methods for digital MRA compensation 有权
    数字MRA补偿的系统和方法

    公开(公告)号：US08904070B2

    公开(公告)日：2014-12-02

    申请号：US13362466

    申请日：2012-01-31

    申请人： Nayak Ratnakar Aravind ,  Yu Liao ,  Haitao Xia

    发明人： Nayak Ratnakar Aravind ,  Yu Liao ,  Haitao Xia

    IPC分类号： G06F13/12 ,  G06F13/38 ,  H03M1/12

    CPC分类号： H03M1/12 ,  G06F13/385

    摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an analog to digital converter circuit, and a magneto-resistive adjustment circuit. The analog to digital converter circuit is operable to convert an input signal into corresponding digital samples. The magneto-resistive adjustment circuit is operable to reduce signal asymmetry in the digital samples due to sensing by a magneto-resistive head to yield a corrected output.

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，讨论了包括：模数转换器电路和磁阻调节电路的数据处理系统。 模数转换器电路可操作以将输入信号转换成对应的数字采样。 磁阻调节电路可操作以由于由磁阻头感测而产生校正输出，从而减少数字采样中的信号不对称性。

    Systems and Methods for Hybrid MRA Compensation
    5.
    发明申请
    Systems and Methods for Hybrid MRA Compensation 审中-公开
    混合MRA补偿的系统和方法

    公开(公告)号：US20130335844A1

    公开(公告)日：2013-12-19

    申请号：US13524462

    申请日：2012-06-15

    申请人： Nayak Ratnakar Aravind ,  Yu Liao ,  Haitao Xia

    发明人： Nayak Ratnakar Aravind ,  Yu Liao ,  Haitao Xia

    IPC分类号： G11B5/027 ,  G11B5/035

    CPC分类号： G11B5/09 ,  G11B5/035

    摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an analog to digital converter circuit, and a magneto-resistive adjustment circuit. The analog to digital converter circuit is operable to convert an input signal into corresponding digital samples. The magneto-resistive adjustment circuit is operable to reduce signal asymmetry in the digital samples due to sensing by a magneto-resistive head to yield a corrected output.

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，讨论了包括：模数转换器电路和磁阻调节电路的数据处理系统。 模数转换器电路可操作以将输入信号转换成对应的数字采样。 磁阻调节电路可操作以由于由磁阻头感测而产生校正输出，从而减少数字采样中的信号不对称性。

    LDPC decoder with fractional unsatisfied check quality metric
    7.
    发明授权
    LDPC decoder with fractional unsatisfied check quality metric 有权
    具有分数不满足检验质量度量的LDPC解码器

    公开(公告)号：US08930788B2

    公开(公告)日：2015-01-06

    申请号：US13602463

    申请日：2012-09-04

    申请人： Fan Zhang ,  Ming Jin ,  Wu Chang ,  Haitao Xia

    发明人： Fan Zhang ,  Ming Jin ,  Wu Chang ,  Haitao Xia

    IPC分类号： H03M13/00

    CPC分类号： H03M13/6343 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/1128 ,  H03M13/1171 ,  H03M13/2957 ,  H03M13/658

    摘要： An apparatus includes a low density parity check decoder operable to iteratively generate messages between a plurality of check nodes and variable nodes, and to calculate a fractional quality metric for a data block as it is decoded in the low density parity check decoder based at least in part on perceived values of data in the variable nodes. The fractional unsatisfied check quality metric is a probabilistic determination of a number of unsatisfied parity checks in the low density parity check decoder.

    摘要翻译： 一种装置包括低密度奇偶校验解码器，其可操作以在多个校验节点和可变节点之间迭代地生成消息，并且在低密度奇偶校验解码器中解码时计算数据块的分数质量度量，至少基于 部分变量节点中数据的感知值。 分数不满足的检查质量度量是低密度奇偶校验解码器中的不满足奇偶校验的数量的概率确定。

    Systems and methods for track width determination
    8.
    发明授权
    Systems and methods for track width determination 有权
    轨道宽度确定的系统和方法

    公开(公告)号：US08854752B2

    公开(公告)日：2014-10-07

    申请号：US13100063

    申请日：2011-05-03

    申请人： Ming Jin ,  Haitao Xia

    发明人： Ming Jin ,  Haitao Xia

    IPC分类号： G11B27/36 ,  G11B19/04 ,  G11B20/22

    CPC分类号： G11B27/36 ,  G11B19/045 ,  G11B20/22 ,  G11B2220/2516

    摘要： Various embodiments of the present invention provide systems and methods for read sensor characterization. As an example, a data storage device is disclosed that includes a storage medium, a read/write head assembly disposed in relation to the storage medium, and a track width setting circuit. The track width setting circuit is operable to: write data to at least a first track and a second track on the storage medium, read data from the second track, determine an estimated track offset where interference from the data written to the first track is insubstantial, and modify at least the second track width based at least in part on the estimated track offset. The first track is a first track width and the second track is a second track width.

    摘要翻译： 本发明的各种实施例提供用于读取传感器表征的系统和方法。 作为示例，公开了包括存储介质，相对于存储介质设置的读/写头组件和轨道宽度设置电路的数据存储设备。 轨道宽度设置电路可操作用于：将数据写入存储介质上的至少第一磁道和第二磁道，从第二磁道读取数据，确定估计的磁道偏移量，其中写入第一磁道的数据的干扰是非实质的 并且至少部分地基于估计的轨道偏移来修改至少第二轨道宽度。 第一轨道是第一轨道宽度，第二轨道是第二轨道宽度。