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公开(公告)号：US20110029691A1
公开(公告)日：2011-02-03
申请号：US12534564
申请日：2009-08-03
申请人： Rafael Castro Scorsi , Neil S. Feiereisel , Glen O. Sescila, III , Craig M. Conway , Brian Keith Odom , M. Dean Brockhausen, JR.
发明人： Rafael Castro Scorsi , Neil S. Feiereisel , Glen O. Sescila, III , Craig M. Conway , Brian Keith Odom , M. Dean Brockhausen, JR.
IPC分类号： G06F3/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： Provided in some embodiment is a computer system, including a first peripheral device, having a first external data input, a first peripheral storage device to store the measurement data, a first peripheral device output to couple to a system interconnect of the computer system. The first peripheral device capable of receiving measurement data via the external data input the first peripheral device capable of transferring at least a portion of the measurement data to a second peripheral device of the computer system via the system interconnect, and where the second peripheral device is capable of processing at least a portion of the measurement data transferred to the second peripheral device.
摘要翻译： 在一些实施例中提供了一种计算机系统，包括具有第一外部数据输入的第一外围设备，用于存储测量数据的第一外围存储设备，耦合到计算机系统的系统互连的第一外围设备输出。 第一外围设备能够经由外部数据接收测量数据，第一外围设备能够经由系统互连将至少一部分测量数据传送到计算机系统的第二外围设备，并且其中第二外围设备是 能够处理传送到第二外围设备的测量数据的至少一部分。
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公开(公告)号：US08458371B2
公开(公告)日：2013-06-04
申请号：US12534564
申请日：2009-08-03
申请人： Rafael Castro Scorsi , Neil S. Feiereisel , Glen O. Sescila, III , Craig M. Conway , Brian Keith Odom , M. Dean Brockhausen, Jr.
发明人： Rafael Castro Scorsi , Neil S. Feiereisel , Glen O. Sescila, III , Craig M. Conway , Brian Keith Odom , M. Dean Brockhausen, Jr.
IPC分类号： G06F3/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： Provided in some embodiment is a computer system, including a first peripheral device, having a first external data input, a first peripheral storage device to store the measurement data, a first peripheral device output to couple to a system interconnect of the computer system. The first peripheral device capable of receiving measurement data via the external data input the first peripheral device capable of transferring at least a portion of the measurement data to a second peripheral device of the computer system via the system interconnect, and where the second peripheral device is capable of processing at least a portion of the measurement data transferred to the second peripheral device.
摘要翻译： 在一些实施例中提供了一种计算机系统，包括具有第一外部数据输入的第一外围设备，用于存储测量数据的第一外围存储设备，耦合到计算机系统的系统互连的第一外围设备输出。 第一外围设备能够经由外部数据接收测量数据，第一外围设备能够经由系统互连将至少一部分测量数据传送到计算机系统的第二外围设备，并且其中第二外围设备是 能够处理传送到第二外围设备的测量数据的至少一部分。
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公开(公告)号：US20110029709A1
公开(公告)日：2011-02-03
申请号：US12534492
申请日：2009-08-03
申请人： Neil S. Feiereisel , Glen O. Sescila, III , Craig M. Conway , Brian Keith Odom , M. Dean Brockhausen, JR.
发明人： Neil S. Feiereisel , Glen O. Sescila, III , Craig M. Conway , Brian Keith Odom , M. Dean Brockhausen, JR.
CPC分类号： G06F13/385 , G06F2213/0026
摘要： Provided is a method of streaming transfer of data between a plurality of devices of a computer system. The method includes providing data to be sent from a source device to a target device and includes receiving, at the source device, one or more transfer credits from the target device. A transfer credit may be indicative of an amount of data that the target device is authorizing to be sent to the target device. The method also includes determining whether or not an accumulated transfer credit value satisfies a threshold value. If the accumulated transfer credit value satisfies the threshold value, the source device sends data to the target device and modifies the accumulated transfer credit value based on a quantity of data sent. If the accumulated transfer credit value does not satisfy the threshold value the source device does not send data to the target device.
摘要翻译： 提供了一种在计算机系统的多个设备之间流传输数据的方法。 该方法包括提供要从源设备发送到目标设备的数据，并且包括在源设备处从目标设备接收一个或多个传送信用。 转移信用可以指示目标设备授权发送到目标设备的数据量。 该方法还包括确定累积的转移信用值是否满足阈值。 如果积累的转移信用值满足阈值，则源设备将数据发送到目标设备，并根据发送的数据量来修改累计转账信用值。 如果累积的转移信用值不满足阈值，则源设备不向目标设备发送数据。
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公开(公告)号：US08307136B2
公开(公告)日：2012-11-06
申请号：US12534492
申请日：2009-08-03
申请人： Neil S. Feiereisel , Glen O. Sescila, III , Craig M. Conway , Brian Keith Odom , M. Dean Brockhausen, Jr.
发明人： Neil S. Feiereisel , Glen O. Sescila, III , Craig M. Conway , Brian Keith Odom , M. Dean Brockhausen, Jr.
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F2213/0026
摘要： Provided is a method of streaming transfer of data between a plurality of devices of a computer system. The method includes providing data to be sent from a source device to a target device and includes receiving, at the source device, one or more transfer credits from the target device. A transfer credit may be indicative of an amount of data that the target device is authorizing to be sent to the target device. The method also includes determining whether or not an accumulated transfer credit value satisfies a threshold value. If the accumulated transfer credit value satisfies the threshold value, the source device sends data to the target device and modifies the accumulated transfer credit value based on a quantity of data sent. If the accumulated transfer credit value does not satisfy the threshold value the source device does not send data to the target device.
摘要翻译： 提供了一种在计算机系统的多个设备之间流传输数据的方法。 该方法包括提供要从源设备发送到目标设备的数据，并且包括在源设备处从目标设备接收一个或多个传送信用。 转移信用可以指示目标设备授权发送到目标设备的数据量。 该方法还包括确定累积的转移信用值是否满足阈值。 如果积累的转移信用值满足阈值，则源设备将数据发送到目标设备，并根据发送的数据量来修改累计转账信用值。 如果累积的转移信用值不满足阈值，则源设备不向目标设备发送数据。
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5.发明授权
公开(公告)号：US5875313A
公开(公告)日：1999-02-23
申请号：US826920
申请日：1997-04-08
CPC分类号： H04L12/40123 , G06F13/4059
摘要： A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 1394 request and response packets with the host computer using the translated 1394 memory address. The translator also translates 1394 memory addresses of 1394 request packets received from the host computer into PCI cycle addresses and performs data transfers between the PCI device and host computer by initiating PCI bus cycles targeted at the PCI device using the translated PCI bus cycle addresses. The translator posts data from sequential PCI bus write cycles initiated by the PCI device into a write-posting FIFO until granted ownership of the 1394 bus. The translator combines the PCI write cycle data into a single IEEE 1394 write request packet and transmits the packet on the 1394 bus to the host computer. The translator, if configured to a first mode, pipelines subsequent PCI bus write cycles by posting the PCI write cycle data into the write-posting FIFO once reception of the first 1394 write request packet has been acknowledged by the host computer but prior to the host computer responding with status indicating the completion of the write transaction, in particular whether or not a resource conflict occurred. In response to a PCI read cycle initiated by the PCI device, the translator pre-fetches a larger amount of data than specified in the PCI read cycle from the host computer into a pre-fetch FIFO in order to satisfy subsequent PCI read cycles which are in address sequence with the previous PCI read cycle. The translator pre-fetches more data from the host computer once the pre-fetch FIFO becomes a predetermined amount empty in order to pipeline the consumption of the pre-fetch data by the PCI device and the transmission of the pre-fetch data by the host computer to the translator.
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6.发明申请Optimizing the Responsiveness and Throughput of a System Performing Packetized Data Transfers 有权优化执行分组化数据传输的系统的响应性和吞吐量公开(公告)号：US20090100201A1
公开(公告)日：2009-04-16
申请号：US12341438
申请日：2008-12-22
IPC分类号： G06F3/00
CPC分类号： H04L1/24 , H04L43/50 , H04L2001/0094
摘要： A mechanism for managing packetized data transfers in a system including a transmitting and a receiving device. The transmitting device may transmit data to the receiving device in a plurality of packets, each packet a predetermined number of data bytes wide. The transmitting device may include a transfer count unit to maintain a data transfer count based on a number of transmitted data bytes. The receiving device may program the transmitting device with a transfer count mark, which may be a number that corresponds to a specific count of the data transfer count. The transmitting device may calculate a difference between the data transfer count and the transfer count mark. If the difference between the transfer count and the transfer count mark is less than the predetermined number, the transmitting device may transmit a short data packet having less than the predetermined number of data bytes to the receiving device.
摘要翻译： 一种用于在包括发送和接收设备的系统中管理分组化数据传输的机制。 发送设备可以以多个分组向接收设备发送数据，每个分组具有预定数量的数据字节宽。 发送装置可以包括传送计数单元，用于基于发送的数据字节的数量维持数据传送计数。 接收设备可以使用传输计数标记对发送设备进行编程，该传送计数标记可以是对应于数据传送计数的特定计数的数字。 发送装置可以计算数据传送计数和传送计数标记之间的差异。 如果传送计数和传送计数标记之间的差小于预定数量，则发送装置可以向接收装置发送具有小于预定数量的数据字节的短数据包。
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公开(公告)号：US5937175A
公开(公告)日：1999-08-10
申请号：US826925
申请日：1997-04-08
CPC分类号： H04L12/40123 , G06F13/128 , G06F13/4059
摘要： A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 1394 request and response packets with the host computer using the translated 1394 memory address. The translator also translates 1394 memory addresses of 1394 request packets received from the host computer into PCI cycle addresses and performs data transfers between the PCI device and host computer by initiating PCI bus cycles targeted at the PCI device using the translated PCI bus cycle addresses. The translator posts data from sequential PCI bus write cycles initiated by the PCI device into a write-posting FIFO until granted ownership of the 1394 bus. The translator combines the PCI write cycle data into a single IEEE 1394 write request packet and transmits the packet on the 1394 bus to the host computer. The translator, if configured to a first mode, pipelines subsequent PCI bus write cycles by posting the PCI write cycle data into the write-posting FIFO once reception of the first 1394 write request packet has been acknowledged by the host computer but prior to the host computer responding with status indicating the completion of the write transaction, in particular whether or not a resource conflict occurred. In response to a PCI read cycle initiated by the PCI device, the translator pre-fetches a larger amount of data than specified in the PCI read cycle from the host computer into a pre-fetch FIFO in order to satisfy subsequent PCI read cycles which are in address sequence with the previous PCI read cycle. The translator pre-fetches more data from the host computer once the pre-fetch FIFO becomes a predetermined amount empty in order to pipeline the consumption of the pre-fetch data by the PCI device and the transmission of the pre-fetch data by the host computer to the translator.
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8.发明授权Optimizing the responsiveness and throughput of a system performing packetized data transfers 有权优化执行分组化数据传输的系统的响应性和吞吐量公开(公告)号：US07849210B2
公开(公告)日：2010-12-07
申请号：US12341438
申请日：2008-12-22
IPC分类号： G06F15/16
CPC分类号： H04L1/24 , H04L43/50 , H04L2001/0094
摘要： A mechanism for managing packetized data transfers in a system including a transmitting and a receiving device. The transmitting device may transmit data to the receiving device in a plurality of packets, each packet a predetermined number of data bytes wide. The transmitting device may include a transfer count unit to maintain a data transfer count based on a number of transmitted data bytes. The receiving device may program the transmitting device with a transfer count mark, which may be a number that corresponds to a specific count of the data transfer count. The transmitting device may calculate a difference between the data transfer count and the transfer count mark. If the difference between the transfer count and the transfer count mark is less than the predetermined number, the transmitting device may transmit a short data packet having less than the predetermined number of data bytes to the receiving device.
摘要翻译： 一种用于在包括发送和接收设备的系统中管理分组化数据传输的机制。 发送设备可以以多个分组向接收设备发送数据，每个分组具有预定数量的数据字节宽。 发送装置可以包括传送计数单元，用于基于发送的数据字节的数量维持数据传送计数。 接收设备可以使用传输计数标记对发送设备进行编程，该传送计数标记可以是对应于数据传送计数的特定计数的数字。 发送装置可以计算数据传送计数和传送计数标记之间的差异。 如果传送计数和传送计数标记之间的差小于预定数量，则发送装置可以向接收装置发送具有小于预定数量的数据字节的短数据包。
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9.发明授权Method and apparatus for optimizing the responsiveness and throughput of a system performing packetized data transfers using a transfer count mark 有权用于优化使用传送计数标记执行分组化数据传输的系统的响应性和吞吐量的方法和装置公开(公告)号：US07631097B2
公开(公告)日：2009-12-08
申请号：US11186183
申请日：2005-07-21
IPC分类号： G06F15/16
CPC分类号： H04L1/24 , H04L43/50 , H04L2001/0094
摘要： A mechanism for managing packetized data transfers in a system including a transmitting and a receiving device. The transmitting device may transmit data to the receiving device in a plurality of packets, each packet a predetermined number of data bytes wide. The transmitting device may include a transfer count unit to maintain a data transfer count based on a number of transmitted data bytes. The receiving device may program the transmitting device with a transfer count mark, which may be a number that corresponds to a specific count of the data transfer count. The transmitting device may calculate a difference between the data transfer count and the transfer count mark. If the difference between the transfer count and the transfer count mark is less than the predetermined number, the transmitting device may transmit a short data packet having less than the predetermined number of data bytes to the receiving device.
摘要翻译： 一种用于在包括发送和接收设备的系统中管理分组化数据传输的机制。 发送设备可以以多个分组向接收设备发送数据，每个分组具有预定数量的数据字节宽。 发送装置可以包括传送计数单元，用于基于发送的数据字节的数量维持数据传送计数。 接收设备可以使用传输计数标记对发送设备进行编程，该传送计数标记可以是对应于数据传送计数的特定计数的数字。 发送装置可以计算数据传送计数和传送计数标记之间的差异。 如果传送计数和传送计数标记之间的差小于预定数量，则发送装置可以向接收装置发送具有小于预定数量的数据字节的短数据包。
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公开(公告)号：US5953511A
公开(公告)日：1999-09-14
申请号：US835527
申请日：1997-04-08
CPC分类号： H04L12/40123 , G06F13/4027 , G06F13/404 , G06F13/4059
摘要： A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 1394 request and response packets with the host computer using the translated 1394 memory address. The translator also translates 1394 memory addresses of 1394 request packets received from the host computer into PCI cycle addresses and performs data transfers between the PCI device and host computer by initiating PCI bus cycles targeted at the PCI device using the translated PCI bus cycle addresses. The translator posts data from sequential PCI bus write cycles initiated by the PCI device into a write-posting FIFO until granted ownership of the 1394 bus. The translator combines the PCI write cycle data into a single IEEE 1394 write request packet and transmits the packet on the 1394 bus to the host computer. The translator, if configured to a first mode, pipelines subsequent PCI bus write cycles by posting the PCI write cycle data into the write-posting FIFO once reception of the first 1394 write request packet has been acknowledged by the host computer but prior to the host computer responding with status indicating the completion of the write transaction, in particular whether or not a resource conflict occurred. In response to a PCI read cycle initiated by the PCI device, the translator pre-fetches a larger amount of data than specified in the PCI read cycle from the host computer into a pre-fetch FIFO in order to satisfy subsequent PCI read cycles which are in address sequence with the previous PCI read cycle. The translator pre-fetches more data from the host computer once the pre-fetch FIFO becomes a predetermined amount empty in order to pipeline the consumption of the pre-fetch data by the PCI device and the transmission of the pre-fetch data by the host computer to the translator.
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