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公开(公告)号:US10261928B2
公开(公告)日:2019-04-16
申请号:US16018085
申请日:2018-06-26
发明人: Yi-Hung Chen , Yuan-Chin Liu
IPC分类号: G06F13/00 , G06F13/362 , G06F13/40 , H04L7/00
摘要: A wafer-level package includes a first die and a second die that are wafer-level packaged. The first die has a first clock source. The second die has a second clock source. The first clock source generates a clock shared by the first die and the second die. The second clock source, however, does not generate a clock used by any of the first die and the second die.
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2.
公开(公告)号:US20180300272A1
公开(公告)日:2018-10-18
申请号:US16018085
申请日:2018-06-26
发明人: Yi-Hung Chen , Yuan-Chin Liu
IPC分类号: G06F13/362 , H04L7/00 , G06F13/40
CPC分类号: G06F13/362 , G06F13/4022 , H04L7/00 , H04L7/0008 , H04L7/005
摘要: A wafer-level package includes a first die and a second die that are wafer-level packaged. The first die has a first clock source. The second die has a second clock source. The first clock source generates a clock shared by the first die and the second die. The second clock source, however, does not generate a clock used by any of the first die and the second die.
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