公开(公告)号：US10855522B2

公开(公告)日：2020-12-01

申请号：US16190705

申请日：2018-11-14

Applicant: NetApp Inc.

Inventor： William Leo Rollins ,  Daniel John Kolor

IPC: H04L12/24 ,  H04L12/935 ,  H04L12/931

Abstract: Techniques are provided for dual port storage device emulation. A switch is configured with a first virtual switch to provide a first computing device with access a first single port device through a first port and a second port. The switch is configured with a second virtual switch to provide a second computing device with access to a second single port device through a third port and a fourth port. In response to determining that the first computing device has experienced a failure, the first virtual switch and the second virtual switch are reconfigured to provide the second computing device with access to the first single port device through the second port and access to the second single port device through the fourth port. The first computing device is disconnected from accessing the first single port device through the first virtual switch.

公开(公告)号：US20160026589A1

公开(公告)日：2016-01-28

申请号：US14341456

申请日：2014-07-25

Applicant: NetApp, Inc.

Inventor： Daniel John Kolor ,  William Leo Rollins ,  Robert Walker

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A system and method for adaptive bus configuration operable to respond to hardware changes and other configuration changes is disclosed. In an embodiment, the computing system includes a circuit assembly having at least one processing resource coupled to a respective set of bus traces, at least one peripheral device socket coupled to a respective set of bus traces, and a bus switch coupled to the bus traces of the processing resource and the bus traces of the peripheral device. The bus switch implements a set of connections between the bus traces of the processing resource and the bus traces of the peripheral device sockets according to an instruction. The instruction may specify an allocation of peripheral device sockets to processing resources based on the number of installed processing resources so that no peripheral device is connected to a bus without an attached processor.

Abstract translation: 公开了一种用于自适应总线配置的系统和方法，其可操作以响应硬件改变和其他配置变化。 在一个实施例中，计算系统包括具有耦合到相应集合总线迹线的至少一个处理资源的电路组件，耦合到相应集合总线迹线的至少一个外围设备插座以及耦合到总线迹线的总线开关 的处理资源和外围设备的总线轨迹。 总线开关根据指令在处理资源的总线轨迹和外围设备插座的总线轨迹之间实现一组连接。 该指令可以指定外围设备插座的分配，以便基于所安装的处理资源的数量来处理资源，使得没有附加处理器的外围设备连接到总线。

公开(公告)号：US20200052955A1

公开(公告)日：2020-02-13

申请号：US16190705

申请日：2018-11-14

Applicant: NetApp Inc.

Inventor： William Leo Rollins ,  Daniel John Kolor

IPC: H04L12/24 ,  H04L12/931 ,  H04L12/935

Abstract: Techniques are provided for dual port storage device emulation. A switch is configured with a first virtual switch to provide a first computing device with access a first single port device through a first port and a second port. The switch is configured with a second virtual switch to provide a second computing device with access to a second single port device through a third port and a fourth port. In response to determining that the first computing device has experienced a failure, the first virtual switch and the second virtual switch are reconfigured to provide the second computing device with access to the first single port device through the second port and access to the second single port device through the fourth port. The first computing device is disconnected from accessing the first single port device through the first virtual switch.

公开(公告)号：US09836423B2

公开(公告)日：2017-12-05

申请号：US14341456

申请日：2014-07-25

Applicant: NetApp, Inc.

Inventor： Daniel John Kolor ,  William Leo Rollins ,  Robert Walker

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A system and method for adaptive bus configuration operable to respond to hardware changes and other configuration changes is disclosed. In an embodiment, the computing system includes a circuit assembly having at least one processing resource coupled to a respective set of bus traces, at least one peripheral device socket coupled to a respective set of bus traces, and a bus switch coupled to the bus traces of the processing resource and the bus traces of the peripheral device. The bus switch implements a set of connections between the bus traces of the processing resource and the bus traces of the peripheral device sockets according to an instruction. The instruction may specify an allocation of peripheral device sockets to processing resources based on the number of installed processing resources so that no peripheral device is connected to a bus without an attached processor.