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公开(公告)号：US08494038B2
公开(公告)日：2013-07-23
申请号：US12972480
申请日：2010-12-19
IPC分类号： H04B3/46
CPC分类号： H04B3/30 , H04L25/0274
摘要： A receiver circuit detects an eye margin within a differential signal having a true component and a complement component. A transmitter circuit adjusts a phase between the true component and the complement component of the differential signal, based on the eye margin, to improve the eye margin. Improving the eye margin results from a reduction in common mode noise within the differential signal.
摘要翻译： 接收机电路检测具有真实分量和补码分量的差分信号内的眼界。 发射机电路基于眼睛边缘调整差分信号的真实分量和补码分量之间的相位，以改善眼睛边缘。 差分信号中共模噪声的降低导致改善眼余量。
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公开(公告)号：US20120155527A1
公开(公告)日：2012-06-21
申请号：US12972480
申请日：2010-12-19
IPC分类号： H04B3/46
CPC分类号： H04B3/30 , H04L25/0274
摘要： A receiver circuit detects an eye margin within a differential signal having a true component and a complement component. A transmitter circuit adjusts a phase between the true component and the complement component of the differential signal, based on the eye margin, to improve the eye margin. Improving the eye margin results from a reduction in common mode noise within the differential signal
摘要翻译： 接收机电路检测具有真实分量和补码分量的差分信号内的眼界。 发射机电路基于眼睛边缘调整差分信号的真实分量和补码分量之间的相位，以改善眼睛边缘。 差分信号中共模噪声的降低导致改善眼余量
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3.发明授权Laminate capacitor stack inside a printed circuit board for electromagnetic compatibility capacitance 失效用于电磁兼容性电容的印刷电路板内层叠电容器堆叠公开(公告)号：US08492658B2
公开(公告)日：2013-07-23
申请号：US12947562
申请日：2010-11-16
CPC分类号： H05K1/162 , H05K1/0231 , H05K2201/097 , Y10T29/49124 , Y10T29/49165
摘要： An apparatus comprises a multi-layer printed circuit board having at least three conductor layers, a dielectric material layer between each of the conductor layers, and a laminate capacitor stack arranged transversely through the printed circuit board. The laminate capacitor stack comprises: (a) a plurality of conducting patches including a patch in a plurality of the conductor layers, wherein the plurality of patches are aligned in a stack with the dielectric material filling the space between adjacent patches; (b) a first conducting via interconnecting each patch in a first subset of the plurality of patches, wherein the first subset of the plurality of patches are coupled to one of the conductor layers that is at ground potential; and (c) a second conducting via interconnecting each patch in a second subset of the plurality of patches, wherein the second subset of the plurality of patches are coupled to one of the conductor layers that is at power potential, wherein the patches in the first subset are disposed in an alternating pattern with the patches in the second subset.
摘要翻译： 一种装置包括具有至少三个导体层的多层印刷电路板，每个导体层之间的介电材料层和横向布置在印刷电路板上的叠层电容器叠层。 层压电容器堆叠包括：（a）多个导电贴片，包括多个导体层中的贴片，其中多个贴片以堆叠的方式与电介质材料填充相邻贴片之间的空间; （b）第一导电通孔，其互连多个贴片的第一子集中的每个贴片，其中所述多个贴片的第一子集耦合到处于地电位的导体层之一; 和（c）第二导电通孔，其互连多个贴片的第二子集中的每个贴片，其中多个贴片的第二子集耦合到处于功率电位的导体层中的一个，其中第一 子集以与第二子集中的贴片交替模式布置。
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4.发明申请公开(公告)号：US20120118622A1
公开(公告)日：2012-05-17
申请号：US12947562
申请日：2010-11-16
CPC分类号： H05K1/162 , H05K1/0231 , H05K2201/097 , Y10T29/49124 , Y10T29/49165
摘要： An apparatus comprises a multi-layer printed circuit board having at least three conductor layers, a dielectric material layer between each of the conductor layers, and a laminate capacitor stack arranged transversely through the printed circuit board. The laminate capacitor stack comprises: (a) a plurality of conducting patches including a patch in a plurality of the conductor layers, wherein the plurality of patches are aligned in a stack with the dielectric material filling the space between adjacent patches; (b) a first conducting via interconnecting each patch in a first subset of the plurality of patches, wherein the first subset of the plurality of patches are coupled to one of the conductor layers that is at ground potential; and (c) a second conducting via interconnecting each patch in a second subset of the plurality of patches, wherein the second subset of the plurality of patches are coupled to one of the conductor layers that is at power potential, wherein the patches in the first subset are disposed in an alternating pattern with the patches in the second subset.
摘要翻译： 一种装置包括具有至少三个导体层的多层印刷电路板，每个导体层之间的介电材料层和横向布置在印刷电路板上的叠层电容器叠层。 层压电容器堆叠包括：（a）多个导电贴片，包括多个导体层中的贴片，其中多个贴片以堆叠的方式与电介质材料填充相邻贴片之间的空间; （b）第一导电通孔，其互连多个贴片的第一子集中的每个贴片，其中所述多个贴片的第一子集耦合到处于地电位的导体层之一; 和（c）第二导电通孔，其互连多个贴片的第二子集中的每个贴片，其中多个贴片的第二子集耦合到处于功率电位的导体层中的一个，其中第一 子集以与第二子集中的贴片交替模式布置。
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公开(公告)号：US08901946B2
公开(公告)日：2014-12-02
申请号：US12785572
申请日：2010-05-24
CPC分类号： G01R31/2813 , G01R31/2815
摘要： Apparatus and methods for identifying a signal on a printed circuit board (‘PCB’) under test, including an integrated circuit mounted on the PCB, the integrated circuit having a test signal generator that transmits a test signal to an output pin of the integrated circuit, with the output pin connected to a test point on the PCB; the integrated circuit also having signal identification logic that inserts into the test signal, an identifier of the signal; a test probe in contact with the test point; and a signal-identifying controller that receives the test signal and the identifier from the test probe and displays, in dependence upon the identifier, the identity of the signal.
摘要翻译： 用于识别被测PCB板上的信号的装置和方法，包括安装在PCB上的集成电路，该集成电路具有测试信号发生器，该测试信号发生器将测试信号发送到集成电路的输出引脚 ，输出引脚连接到PCB上的测试点; 该集成电路还具有插入到测试信号中的信号识别逻辑，该信号的标识符; 与测试点接触的测试探针; 以及信号识别控制器，其从测试探针接收测试信号和标识符，并根据标识符显示信号的身份。
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公开(公告)号：US20130097412A1
公开(公告)日：2013-04-18
申请号：US13275019
申请日：2011-10-17
申请人： Shiva R. Dasari , Raghuswamyreddy Gundam , Newton P. Liu , Terence Rodrigues , Mehul M. Shah , Robert K. Sloan , Wingcheung Tam , Mark W. Wenning
发明人： Shiva R. Dasari , Raghuswamyreddy Gundam , Newton P. Liu , Terence Rodrigues , Mehul M. Shah , Robert K. Sloan , Wingcheung Tam , Mark W. Wenning
IPC分类号： G06F9/445
CPC分类号： G06F9/4405
摘要： Methods, apparatuses, and computer program products for performing a boot sequence in a multi-processor system are provided. Embodiments include: in response to detecting initiation of a boot sequence of the multi-processor system, initializing, by a bootstrap processor (BSP), BSP memory associated with the BSP and initializing, by an application processor, memory associated with the application processor; determining, by the BSP, whether the initialization of the BSP memory is completed; and if the initialization of the BSP memory is completed, loading, by the BSP, an operating system on the BSP memory regardless of whether the application processor has completed initialization of the memory associated with the application processor.
摘要翻译： 提供了用于在多处理器系统中执行引导顺序的方法，装置和计算机程序产品。 实施例包括：响应于检测到多处理器系统的引导序列的启动，由引导处理器（BSP）初始化与BSP相关联的BSP存储器并由应用处理器初始化与应用处理器相关联的存储器; 由BSP确定BSP存储器的初始化是否完成; 并且如果BSP存储器的初始化完成，则由BSP加载BSP存储器上的操作系统，而不管应用处理器是否已经完成与应用处理器相关联的存储器的初始化。
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公开(公告)号：US20110279138A1
公开(公告)日：2011-11-17
申请号：US12780333
申请日：2010-05-14
IPC分类号： G01R31/02 , G01R31/304
CPC分类号： G01R31/2843 , G01R31/2806 , G01R31/2834 , G01R31/2839 , G01R31/3025
摘要： Identifying a signal on a printed circuit board (‘PCB’) under test, including a test probe with a radio transmitter and transmitter antenna, the test probe positioned with the transmitter antenna at a test point on the PCB, the test probe transmitting a radio signal; at least two radio receivers, each receiver having a receiver antenna, each receiver antenna positioned at predetermined, separate physical locations with respect to the PCB, the receivers coupled to at least one signal strength meter, each receiver receiving the transmitted radio signal; and a signal-identifying controller connected to the signal strength meter, the signal-identifying controller reading, from the signal strength meter, signal strengths of the transmitted radio signal as received at the radio receivers; determining, in dependence upon the read signal strengths, a test signal identifier; and displaying the test signal identifier.
摘要翻译： 识别在被测试的印刷电路板（“PCB”）上的信号，包括带有无线电发射机和发射机天线的测试探头，测试探头定位在发射机天线位于PCB的测试点，测试探头发射无线电 信号; 至少两个无线电接收机，每个接收机具有接收机天线，每个接收机天线相对于所述PCB定位在预定的分离的物理位置，所述接收机耦合到至少一个信号强度计，每个接收机接收所传输的无线电信号; 信号识别控制器，连接到信号强度计，信号识别控制器从信号强度计读取在无线电接收机处接收的发射的无线电信号的信号强度; 根据读取的信号强度来确定测试信号标识符; 并显示测试信号标识符。
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公开(公告)号：US07734955B2
公开(公告)日：2010-06-08
申请号：US12246748
申请日：2008-10-07
申请人： Charles R. Dart , Edmund Sutherland Gamble , Gary Anthony Jansma , Terence Rodrigues , Robert Joseph Ruckriegel , Bruce James Wilkie
发明人： Charles R. Dart , Edmund Sutherland Gamble , Gary Anthony Jansma , Terence Rodrigues , Robert Joseph Ruckriegel , Bruce James Wilkie
IPC分类号： G06F11/00
CPC分类号： G11C29/02 , G11C5/147 , G11C29/021
摘要： A method and system for improving Field Replacement Unit (FRU) isolation in memory sub-systems by monitoring Voltage Regulator Module (VRM) induced memory errors. A comparator compares the output voltage coming from the VRM to memory. If the comparator detects a VRM output voltage transient that is outside a rated threshold, then a counter is increased by one. If the counter exceeds a count threshold, a VRM error is posted. If a memory failure occurs within a predetermined period of time, then the VRM error pinpoints the VRM output voltage transient as being the likely cause of the memory failure.
摘要翻译： 通过监控电压调节器模块（VRM）引起的内存错误，改善了存储器子系统中的现场替换单元（FRU）隔离的方法和系统。 比较器将来自VRM的输出电压与存储器进行比较。 如果比较器检测到超出额定阈值的VRM输出电压瞬变，则计数器增加1。 如果计数器超过计数阈值，则发布VRM错误。 如果在预定时间内出现内存故障，则VRM错误将VRM输出电压瞬变定位为存储器故障的可能原因。
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9.发明申请Method and topology for improving signal quality on high speed, multi-drop busses 有权用于提高高速多点总线信号质量的方法和拓扑公开(公告)号：US20050253621A1
公开(公告)日：2005-11-17
申请号：US10845897
申请日：2004-05-14
申请人： Edmund Gamble , Terence Rodrigues , Leon Wu
发明人： Edmund Gamble , Terence Rodrigues , Leon Wu
IPC分类号： H03K19/003 , H04L25/08
CPC分类号： H04L25/08
摘要： Aspects for improving signal quality on high speed, multi-drop busses are described. The aspects include coupling a source device directly to multiple load devices, wherein there are no resistance components coupled in series between the source device and the multiple load devices. The aspects further include providing a spacing arrangement for the multiple load devices, wherein negative reflections are delayed to minimize deleterious efforts from the negative reflections. Through the present invention, the modified version of a commonly used bus topology achieves extended voltage timing margins in a high speed, multi-drop bus in a straightforward and efficient manner.
摘要翻译： 描述了提高高速，多点总线信号质量的方面。 这些方面包括将源设备直接耦合到多个负载设备，其中在源设备和多个负载设备之间没有串联耦合的电阻元件。 这些方面还包括提供用于多个负载装置的间隔布置，其中延迟负反射以使来自负反射的有害努力最小化。 通过本发明，常用总线拓扑的修改版本以直接和有效的方式实现了高速，多点总线中的延长的电压定时裕度。
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公开(公告)号：US09552330B2
公开(公告)日：2017-01-24
申请号：US13428383
申请日：2012-03-23
申请人： Raghuswamyreddy Gundam , Newton P. Liu , Douglas W. Oliver , Terence Rodrigues , Wingcheung Tam
发明人： Raghuswamyreddy Gundam , Newton P. Liu , Douglas W. Oliver , Terence Rodrigues , Wingcheung Tam
IPC分类号： G06F17/21
CPC分类号： G06F17/211
摘要： Methods, apparatuses, and computer program products for indicating a page number of an active document page within a document are provided. Embodiments include detecting, by a presentation controller, activation of a document page on a presentation device; in response to detecting the activation of the document page on the presentation device, tracking, by the presentation controller, an amount of time that the document page is consecutively active on the presentation device; determining, by the presentation controller, that the amount of time that the document page is consecutively active on the presentation device exceeds a predetermined threshold; and in response to determining that the predetermined threshold has been exceeded, providing to a target source, by the presentation controller, an output indicating a page number of the document page while the document page is active on the presentation device.
摘要翻译： 提供了用于指示文档内的活动文档页面的页面号的方法，装置和计算机程序产品。 实施例包括由呈现控制器检测在呈现设备上的文档页面的激活; 响应于检测到呈现设备上的文档页面的激活，由呈现控制器跟踪文档页面在呈现设备上连续活动的时间量; 由所述呈现控制器确定所述文档页面在所述呈现设备上连续活动的时间量超过预定阈值; 并且响应于确定已经超过所述预定阈值，通过所述呈现控制器向所述目标源提供指示所述文档页面在所述呈现设备上处于活动状态时的所述文档页面的页码的输出。
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