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公开(公告)号:US07566915B2
公开(公告)日:2009-07-28
申请号:US11648250
申请日:2006-12-29
IPC分类号: H01L29/74
CPC分类号: H01L23/585 , H01L22/32 , H01L23/3178 , H01L23/3192 , H01L23/562 , H01L2924/0002 , H01L2924/09701 , Y10S148/07 , H01L2924/00
摘要: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
摘要翻译: 本发明的一个实施例是一种防止半导体器件可靠性故障的技术。 在具有顶部金属层的保护环上的聚酰亚胺层中图案化沟槽。 钝化层在沟槽的底部蚀刻。 在蚀刻的钝化层上的沟槽上沉积覆盖层。 覆盖层和顶部金属层形成机械强界面以防止裂纹扩展。
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公开(公告)号:US20100187528A1
公开(公告)日:2010-07-29
申请号:US12727010
申请日:2010-03-18
IPC分类号: H01L23/48
CPC分类号: H01L23/585 , H01L22/32 , H01L23/3178 , H01L23/3192 , H01L23/562 , H01L2924/0002 , H01L2924/09701 , Y10S148/07 , H01L2924/00
摘要: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
摘要翻译: 本发明的一个实施例是一种防止半导体器件可靠性故障的技术。 在具有顶部金属层的保护环上的聚酰亚胺层中图案化沟槽。 钝化层在沟槽的底部蚀刻。 在蚀刻的钝化层上的沟槽上沉积覆盖层。 封盖层和顶部金属层形成机械强界面以防止裂纹扩展。
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公开(公告)号:US20080157284A1
公开(公告)日:2008-07-03
申请号:US11648250
申请日:2006-12-29
CPC分类号: H01L23/585 , H01L22/32 , H01L23/3178 , H01L23/3192 , H01L23/562 , H01L2924/0002 , H01L2924/09701 , Y10S148/07 , H01L2924/00
摘要: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
摘要翻译: 本发明的一个实施例是一种防止半导体器件可靠性故障的技术。 在具有顶部金属层的保护环上的聚酰亚胺层中图案化沟槽。 钝化层在沟槽的底部蚀刻。 在蚀刻的钝化层上的沟槽上沉积覆盖层。 封盖层和顶部金属层形成机械强界面以防止裂纹扩展。
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公开(公告)号:US07972909B2
公开(公告)日:2011-07-05
申请号:US12425708
申请日:2009-04-17
IPC分类号: H01L21/4763
CPC分类号: H01L23/585 , H01L22/32 , H01L23/3178 , H01L23/3192 , H01L23/562 , H01L2924/0002 , H01L2924/09701 , Y10S148/07 , H01L2924/00
摘要: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
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公开(公告)号:US20090200548A1
公开(公告)日:2009-08-13
申请号:US12425708
申请日:2009-04-17
IPC分类号: H01L29/06 , H01L21/768 , H01L21/302 , H01L23/58
CPC分类号: H01L23/585 , H01L22/32 , H01L23/3178 , H01L23/3192 , H01L23/562 , H01L2924/0002 , H01L2924/09701 , Y10S148/07 , H01L2924/00
摘要: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
摘要翻译: 本发明的一个实施例是一种防止半导体器件可靠性故障的技术。 在具有顶部金属层的保护环上的聚酰亚胺层中图案化沟槽。 钝化层在沟槽的底部蚀刻。 在蚀刻的钝化层上的沟槽上沉积覆盖层。 封盖层和顶部金属层形成机械强界面以防止裂纹扩展。
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公开(公告)号:US07968976B2
公开(公告)日:2011-06-28
申请号:US12727010
申请日:2010-03-18
IPC分类号: H01L23/58
CPC分类号: H01L23/585 , H01L22/32 , H01L23/3178 , H01L23/3192 , H01L23/562 , H01L2924/0002 , H01L2924/09701 , Y10S148/07 , H01L2924/00
摘要: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
摘要翻译: 本发明的一个实施例是一种防止半导体器件可靠性故障的技术。 在具有顶部金属层的保护环上的聚酰亚胺层中图案化沟槽。 钝化层在沟槽的底部蚀刻。 在蚀刻的钝化层上的沟槽上沉积覆盖层。 封盖层和顶部金属层形成机械强界面以防止裂纹扩展。
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