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    Varactor with halo implant regions of opposite polarity
    5.
    发明申请
    Varactor with halo implant regions of opposite polarity 审中-公开
    具有相反极性的晕圈植入区域的变形反应器

    公开(公告)号：US20080079051A1

    公开(公告)日：2008-04-03

    申请号：US11529943

    申请日：2006-09-29

    申请人： Luo Yuan ,  Derchang Kau ,  Wei-Kai Shih ,  Shafqat Ahmed ,  Brian K. Armstrong

    发明人： Luo Yuan ,  Derchang Kau ,  Wei-Kai Shih ,  Shafqat Ahmed ,  Brian K. Armstrong

    IPC分类号： H01L29/94 ,  H01L21/20

    CPC分类号： H01L29/7833 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/6659

    摘要： A metal oxide semiconductor varactor may be formed with HALO implants regions having an opposite polarity from the polarity of the well of the varactor. The HALO implant regions can be angled away from the source and drain. The HALO implant regions can stop the depletion from continuing as the bias voltage applied to the gate continues to increase. Stopping that depletion can create a constant capacitance when the varactor is in a depletion bias.

    摘要翻译： 金属氧化物半导体变容二极管可以形成为具有与变容二极管的极性相反极性的HALO注入区域。 HALO植入区域可以远离源极和漏极成角度。 随着施加到栅极的偏置电压继续增加，HALO注入区域可以阻止耗尽继续。 当变容二极管处于耗尽偏压时，停止耗尽可产生恒定电容。

    Isolated P-well architecture for a memory device
    6.
    发明授权
    Isolated P-well architecture for a memory device 有权
    用于存储器件的隔离P-阱结构

    公开(公告)号：US07920419B2

    公开(公告)日：2011-04-05

    申请号：US12362914

    申请日：2009-01-30

    申请人： Prashant Damle ,  Krishna Parat ,  Shafqat Ahmed

    发明人： Prashant Damle ,  Krishna Parat ,  Shafqat Ahmed

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/3427 ,  H01L27/11519 ,  H01L27/11524

    摘要： A memory device and a method to prevent or reduce program disturb by isolating P-wells of strings in a non-volatile memory array. During a program operation, the isolated P-wells may be coupled to corresponding bitlines, which may be selected or inhibited, and may be at different voltages. During erase, read, and verify operations, the isolated P-wells may be coupled to source.

    摘要翻译： 一种存储器件和通过将非易失性存储器阵列中的P阱分离来防止或减少编程干扰的方法。 在编程操作期间，分离的P阱可以耦合到可以被选择或禁止的相应位线，并且可以处于不同的电压。 在擦除，读取和验证操作期间，隔离的P阱可以耦合到源。

    Programmable read only memory in CMOS process flow
    9.
    发明授权
    Programmable read only memory in CMOS process flow 有权

    公开(公告)号：US06495881B1

    公开(公告)日：2002-12-17

    申请号：US10012835

    申请日：2001-10-22

    申请人： Shafqat Ahmed ,  Hemanshu D. Bhatt ,  Charles E. May ,  Robindranath Banerjee

    发明人： Shafqat Ahmed ,  Hemanshu D. Bhatt ,  Charles E. May ,  Robindranath Banerjee

    IPC分类号： H01L29788

    CPC分类号： H01L27/112 ,  H01L21/8238

    摘要： An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The top electrode material layer and the capacitive material layer are removed to substantially the level of the upper surface of the protective material layer, thereby leaving the top electrode layer and the capacitive material layer overlying the gate electrodes for the selected portion of the complementary metal oxide semiconductor devices. In this manner, capacitors are formed from the top electrode material layer, the capacitive material layer, and the gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The improved process further includes forming nonvolatile memory devices from the selected portion of the complementary metal oxide semiconductor devices, and forming logic devices of the complementary metal oxide semiconductor devices that are not included in the selected portion of the complementary metal oxide semiconductor devices. Fuses are formed in associated with a portion of the nonvolatile memory devices to form read only memory devices of the fused portion of the nonvolatile memory devices.

    INDEPENDENT WELL BIAS MANAGEMENT IN A MEMORY DEVICE
    10.
    发明申请
    INDEPENDENT WELL BIAS MANAGEMENT IN A MEMORY DEVICE 有权
    在存储设备中独立的良好BIAS管理

    公开(公告)号：US20110090739A1

    公开(公告)日：2011-04-21

    申请号：US12582458

    申请日：2009-10-20

    申请人： Akira Goda ,  Tomoharu Tanaka ,  Krishna Parat ,  Prashant Damle ,  Shafqat Ahmed

    发明人： Akira Goda ,  Tomoharu Tanaka ,  Krishna Parat ,  Prashant Damle ,  Shafqat Ahmed

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C16/0483

    摘要： Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.

    摘要翻译： 提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。 根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。 响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。