公开(公告)号：US07848145B2

公开(公告)日：2010-12-07

申请号：US11691901

申请日：2007-03-27

Applicant: Nima Mokhlesi ,  Roy Scheuerlein

Inventor： Nima Mokhlesi ,  Roy Scheuerlein

IPC: G11C16/04 ,  G11C5/02 ,  G11C5/06

CPC classification number: H01L29/7926 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792

Abstract: A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell, a select transistor, a first word line of the first memory cell, a second word line of the second memory cell, a bit line, a source line, and a select gate line of the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.

Abstract translation: 单片三维NAND串包括位于第二存储单元上的第一存储单元，选择晶体管，第一存储单元的第一字线，第二存储单元的第二字线，位线，源极线 ，以及选择晶体管的选择栅极线。 第一和第二字线不平行于位线，并且第一和第二字线平行于源极线和选择栅极线中的至少一个延伸。

公开(公告)号：US07514321B2

公开(公告)日：2009-04-07

申请号：US11691840

申请日：2007-03-27

Applicant: Nima Mokhlesi ,  Roy Scheuerlein

Inventor： Nima Mokhlesi ,  Roy Scheuerlein

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/11568 ,  H01L27/11582

Abstract: A method of making a monolithic, three dimensional NAND string, includes forming a semiconductor active region of a first memory cell over a semiconductor active region of a second memory cell. The semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. The semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.

Abstract translation: 制造单片三维NAND串的方法包括在第二存储单元的半导体有源区上形成第一存储单元的半导体有源区。 第一存储单元的半导体有源区是从上方观察时具有正方形或矩形截面的第一柱，第一柱是位于第二导电型半导体区之间的第一导电型半导体区。 第二存储单元的半导体有源区是当从上方观察时具有正方形或矩形横截面的第二柱，位于第一柱下方的第二柱，第二柱是位于第二导电型半导体 地区。 第一柱中的一个第二导电类型半导体区域接触第二柱中的一个第二导电类型半导体区域。

公开(公告)号：US20080242008A1

公开(公告)日：2008-10-02

申请号：US11691885

申请日：2007-03-27

Applicant: Nima Mokhlesi ,  Roy Scheuerlein

Inventor： Nima Mokhlesi ,  Roy Scheuerlein

IPC: H01L21/77

CPC classification number: H01L27/11568 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11582

Abstract: A method of making a monolithic, three dimensional NAND string, includes forming a select transistor, forming a first memory cell over a second memory cell, forming a first word line for the first memory cell, forming a second word line for the second memory cell, forming a bit line, forming a source line, and forming a select gate line for the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.

Abstract translation: 制造单片三维NAND串的方法包括形成选择晶体管，在第二存储单元上形成第一存储单元，形成第一存储单元的第一字线，形成用于第二存储单元的第二字线 形成位线，形成源极线，并形成用于选择晶体管的选择栅极线。 第一和第二字线不平行于位线，并且第一和第二字线平行于源极线和选择栅极线中的至少一个延伸。

公开(公告)号：US07575973B2

公开(公告)日：2009-08-18

申请号：US11691917

申请日：2007-03-27

Applicant: Nima Mokhlesi ,  Roy Scheuerlein

Inventor： Nima Mokhlesi ,  Roy Scheuerlein

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/11568 ,  H01L27/11582

Abstract: A method of making a monolithic, three dimensional NAND string including a first memory cell located over a second memory cell, includes growing a semiconductor active region of second memory cell, and epitaxially growing a semiconductor active region of the first memory cell on the semiconductor active region of the second memory cell in a different growth step from the step of growing the semiconductor active region of second memory cell.

Abstract translation: 一种制造包括位于第二存储单元之上的第一存储单元的单片三维NAND串的方法包括：生长第二存储单元的半导体有源区，并且在半导体激活时外延生长第一存储单元的半导体有源区 与第二存储单元的半导体有源区的生长步骤不同的生长步骤中的第二存储单元的区域。

公开(公告)号：US07745265B2

公开(公告)日：2010-06-29

申请号：US11691885

申请日：2007-03-27

Applicant: Nima Mokhlesi ,  Roy Scheuerlein

Inventor： Nima Mokhlesi ,  Roy Scheuerlein

IPC: H01L21/82

CPC classification number: H01L27/11568 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11582

Abstract: A method of making a monolithic, three dimensional NAND string, includes forming a select transistor, forming a first memory cell over a second memory cell, forming a first word line for the first memory cell, forming a second word line for the second memory cell, forming a bit line, forming a source line, and forming a select gate line for the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.

Abstract translation: 制造单片三维NAND串的方法包括形成选择晶体管，在第二存储单元上形成第一存储单元，形成第一存储单元的第一字线，形成用于第二存储单元的第二字线 形成位线，形成源极线，并形成用于选择晶体管的选择栅极线。 第一和第二字线不平行于位线，并且第一和第二字线平行于源极线和选择栅极线中的至少一个延伸。

公开(公告)号：US20080242028A1

公开(公告)日：2008-10-02

申请号：US11691917

申请日：2007-03-27

Applicant: Nima Mokhlesi ,  Roy Scheuerlein

Inventor： Nima Mokhlesi ,  Roy Scheuerlein

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/11568 ,  H01L27/11582

Abstract: A method of making a monolithic, three dimensional NAND string including a first memory cell located over a second memory cell, includes growing a semiconductor active region of second memory cell, and epitaxially growing a semiconductor active region of the first memory cell on the semiconductor active region of the second memory cell in a different growth step from the step of growing the semiconductor active region of second memory cell.

Abstract translation: 一种制造包括位于第二存储单元之上的第一存储单元的单片三维NAND串的方法包括：生长第二存储单元的半导体有源区，并且在半导体激活时外延生长第一存储单元的半导体有源区 与第二存储单元的半导体有源区的生长步骤不同的生长步骤中的第二存储单元的区域。

公开(公告)号：US20080239818A1

公开(公告)日：2008-10-02

申请号：US11691901

申请日：2007-03-27

Applicant: Nima Mokhlesi ,  Roy Scheuerlein

Inventor： Nima Mokhlesi ,  Roy Scheuerlein

IPC: G11C11/34

CPC classification number: H01L29/7926 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792

Abstract: A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell, a select transistor, a first word line of the first memory cell, a second word line of the second memory cell, a bit line, a source line, and a select gate line of the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.

Abstract translation: 单片三维NAND串包括位于第二存储单元上的第一存储单元，选择晶体管，第一存储单元的第一字线，第二存储单元的第二字线，位线，源极线 ，以及选择晶体管的选择栅极线。 第一字线和第二字线不平行于位线，并且第一和第二字线平行于源极线和选择栅极线中的至少一个延伸。

公开(公告)号：US07851851B2

公开(公告)日：2010-12-14

申请号：US11691939

申请日：2007-03-27

Applicant: Nima Mokhlesi ,  Roy Scheuerlein

Inventor： Nima Mokhlesi ,  Roy Scheuerlein

IPC: H01L29/792

CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/7827 ,  H01L29/792 ,  H01L29/7926

Abstract: A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell.

Abstract translation: 单片三维NAND串包括位于第二存储单元上的第一存储单元。 外部在第二存储单元的半导体有源区上形成第一存储单元的半导体有源区，使得在第一存储单元的半导体有源区和第二存储单元的半导体有源区之间存在限定的边界。

公开(公告)号：US07808038B2

公开(公告)日：2010-10-05

申请号：US11691858

申请日：2007-03-27

Applicant: Nima Mokhlesi ,  Roy Scheuerlein

Inventor： Nima Mokhlesi ,  Roy Scheuerlein

IPC: H01L29/792

CPC classification number: H01L27/115 ,  H01L27/11556 ,  H01L27/11568

Abstract: A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. A semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.

Abstract translation: 单片三维NAND串包括位于第二存储单元上的第一存储单元。 第一存储单元的半导体有源区是从上方观察时具有正方形或矩形截面的第一柱，第一柱是位于第二导电型半导体区之间的第一导电型半导体区。 第二存储单元的半导体有源区是当从上方观察时具有正方形或矩形横截面的第二柱，位于第一柱下方的第二柱，第二柱是位于第二导电型半导体 地区。 第一柱中的一个第二导电类型半导体区域接触第二柱中的一个第二导电类型半导体区域。

公开(公告)号：US20080237698A1

公开(公告)日：2008-10-02

申请号：US11691858

申请日：2007-03-27

Applicant: Nima Mokhlesi ,  Roy Scheuerlein

Inventor： Nima Mokhlesi ,  Roy Scheuerlein

IPC: H01L29/792

CPC classification number: H01L27/115 ,  H01L27/11556 ,  H01L27/11568

Abstract: A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. A semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.

Abstract translation: 单片三维NAND串包括位于第二存储单元上的第一存储单元。 第一存储单元的半导体有源区是从上方观察时具有正方形或矩形截面的第一柱，第一柱是位于第二导电型半导体区之间的第一导电型半导体区。 第二存储单元的半导体有源区是当从上方观察时具有正方形或矩形横截面的第二柱，位于第一柱下方的第二柱，第二柱是位于第二导电型半导体 地区。 第一柱中的一个第二导电类型半导体区域接触第二柱中的一个第二导电类型半导体区域。