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1.发明申请System and method for preventing deadlock in richly-connected multi-processor computer system using dynamic assignment of virtual channels 失效使用虚拟通道的动态分配来防止富连接多处理器计算机系统中的死锁的系统和方法公开(公告)号：US20080107106A1
公开(公告)日：2008-05-08
申请号：US11594426
申请日：2006-11-08
IPC分类号： H04L12/56
CPC分类号： G06F15/17381 , H04L47/10 , H04L47/11
摘要： Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Each link in the interconnection topology is associated with a set of virtual channels. Each virtual channel has corresponding communication buffers to store communication data and each virtual channel has an associated virtual channel identifier. Each communication between a source processing node and a target processing node is assigned an initial virtual channel to convey the communication from the source processing node. At an intermediate processing node, a different virtual channel is assigned to convey the communication toward the target processing node, in accordance with pre-defined rules to avoid a cycle of dependency of communication buffer resources.
摘要翻译： 使用虚拟通道的动态分配来防止富连接多处理器计算机系统中的死锁的系统和方法。 在具有通过定义的互连拓扑互连的大量多个处理节点的多处理器计算机系统中，阻止了死锁。 互连拓扑中的每个链路与一组虚拟通道相关联。 每个虚拟通道具有对应的通信缓冲器以存储通信数据，并且每个虚拟通道具有相关联的虚拟通道标识符。 为源处理节点和目标处理节点之间的每个通信被分配初始虚拟通道以传送来自源处理节点的通信。 在中间处理节点处，分配不同的虚拟信道以根据预定义的规则向目标处理节点传送通信，以避免通信缓冲器资源的依赖循环。
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2.发明授权System and method for communicating on a richly connected multi-processor computer system using a pool of buffers for dynamic association with a virtual channel 失效用于在富连接的多处理器计算机系统上使用用于与虚拟通道动态关联的缓冲池的通信的系统和方法公开(公告)号：US07773616B2
公开(公告)日：2010-08-10
申请号：US11594405
申请日：2006-11-08
CPC分类号： H04L49/9047 , H04L45/10 , H04L49/90
摘要： Systems and methods for communicating on a richly-connected multiprocessor computer system using a pool of buffers for dynamic association with a virtual channel. Packets are communicated in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology, in which a communication from a source processing node to a target processing node may pass through one or more intermediate nodes en route to the target processing node. A set of virtual channels is associated for each link in the interconnection topology. A first subset of buffers is dedicated for fixed correspondence to virtual channel identifiers, and a second subset of buffers is dedicated for dynamic allocation and assignment to virtual channels.
摘要翻译： 用于在富连接的多处理器计算机系统上进行通信的系统和方法，该缓冲区用于与虚拟通道动态关联。 分组在具有通过定义的互连拓扑互联的大量多个处理节点的多处理器计算机系统中通信，其中从源处理节点到目标处理节点的通信可以通过到目标处理的一个或多个中间节点 节点。 一组虚拟通道与互连拓扑中的每个链路相关联。 缓冲器的第一子集专用于对虚拟信道标识符的固定对应，并且第二子缓存器专用于动态分配和分配给虚拟信道。
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3.发明授权System and method for preventing deadlock in richly-connected multi-processor computer system using dynamic assignment of virtual channels 失效使用虚拟通道的动态分配来防止富连接多处理器计算机系统中的死锁的系统和方法公开(公告)号：US07773618B2
公开(公告)日：2010-08-10
申请号：US11594426
申请日：2006-11-08
CPC分类号： G06F15/17381 , H04L47/10 , H04L47/11
摘要： Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Each link in the interconnection topology is associated with a set of virtual channels. Each virtual channel has corresponding communication buffers to store communication data and each virtual channel has an associated virtual channel identifier. Each communication between a source processing node and a target processing node is assigned an initial virtual channel to convey the communication from the source processing node. At an intermediate processing node, a different virtual channel is assigned to convey the communication toward the target processing node, in accordance with pre-defined rules to avoid a cycle of dependency of communication buffer resources.
摘要翻译： 使用虚拟通道的动态分配来防止富连接多处理器计算机系统中的死锁的系统和方法。 在具有通过定义的互连拓扑互连的大量多个处理节点的多处理器计算机系统中，阻止了死锁。 互连拓扑中的每个链路与一组虚拟通道相关联。 每个虚拟通道具有对应的通信缓冲器以存储通信数据，并且每个虚拟通道具有相关联的虚拟通道标识符。 为源处理节点和目标处理节点之间的每个通信被分配初始虚拟通道以传送来自源处理节点的通信。 在中间处理节点处，分配不同的虚拟信道以根据预定义的规则向目标处理节点传送通信，以避免通信缓冲器资源的依赖循环。
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4.发明授权System and method for arbitration for virtual channels to prevent livelock in a richly-connected multi-processor computer system 失效用于虚拟通道仲裁的系统和方法，以防止富连接的多处理器计算机系统中的活动锁定公开(公告)号：US07773617B2
公开(公告)日：2010-08-10
申请号：US11594420
申请日：2006-11-08
CPC分类号： G06F13/1652
摘要： Systems and methods for arbitrating for virtual channels to prevent livelock in richly-connected multiprocessor computer system. Livelock is prevented in a multiprocessor computer system, in which each of a large plurality processing node has input links and egress links. A virtual channel is assigned to convey the communication. Communication data from the plurality of input links is buffered in cross point buffers. A subset of the cross point buffers bids for, and arbitrates, use of the same one egress link. The virtual channel of the selected communication is identified. It is determined whether any of the other communications bidding for use of the egress link are associated with the identified virtual channel and if so whether any communication has been waiting longer than the selected communication. If so, allowing that communication to use the egress link before the selected communication does.
摘要翻译： 用于虚拟通道仲裁的系统和方法，以防止富连接多处理器计算机系统中的活动锁定。 在多处理器计算机系统中防止了Livelock，其中大的多个处理节点中的每一个具有输入链路和出口链路。 分配虚拟通道来传达通信。 来自多个输入链路的通信数据被缓冲在交叉点缓冲器中。 交叉点缓冲区的一个子集为同一个出口链路的出价和仲裁使用。 识别所选通信的虚拟通道。 是否确定使用出口链路的任何其他通信招标是否与所识别的虚拟通道相关联，并且是否任何通信是否等待比选择的通信更长时间。 如果是这样，允许该通信在所选择的通信之前使用出口链路。
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5.发明申请Large scale computing system with multi-lane mesochronous data transfers among computer nodes 审中-公开在计算机节点之间具有多通道同步数据传输的大规模计算系统公开(公告)号：US20080109672A1
公开(公告)日：2008-05-08
申请号：US11594441
申请日：2006-11-08
申请人： Nitin Godiwala , Matthew H. Reilly
发明人： Nitin Godiwala , Matthew H. Reilly
IPC分类号： G06F1/12
CPC分类号： H04L7/0012 , H04J3/0658 , H04J3/0697
摘要： Large scale computing systems with multi-lane mesochronous data transfers among computer nodes. A large scale computing system includes a large plurality of computing nodes interconnected in a predefined topology. Each computing node is controlled by a corresponding clock signal, and the each clock signal has a mesochronous relationship to the clock signals on the other computing nodes. Each connection between nodes is a multi-lane connection, and each lane carries a serial stream of data that is mesochronously related to the other lanes. Each data lane is characterized relative to the other data lanes between the first and second node to determine relative delay in transmission between the first and second nodes. The transmission delays are equalized so that each data lane provides data for processing in the second clock domain in substantial synchronism with the other lanes.
摘要翻译： 在计算机节点之间具有多通道同步数据传输的大规模计算系统。 大规模计算系统包括以预定拓扑互连的大量多个计算节点。 每个计算节点由对应的时钟信号控制，并且每个时钟信号与其他计算节点上的时钟信号具有中间同步关系。 节点之间的每个连接都是多通道连接，每个通道都携带与其他通道中间相关的串行数据流。 每个数据通道相对于第一和第二节点之间的其他数据通道进行表征，以确定第一和第二节点之间的传输中的相对延迟。 传输延迟被均衡，使得每个数据通道提供用于在第二时钟域中与其他通道基本同步的处理的数据。
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6.发明申请System and method for arbitration for virtual channels to prevent livelock in a richly-connected multi-processor computer system 失效用于虚拟通道仲裁的系统和方法，以防止富连接的多处理器计算机系统中的活动锁定公开(公告)号：US20080109586A1
公开(公告)日：2008-05-08
申请号：US11594420
申请日：2006-11-08
IPC分类号： G06F13/14
CPC分类号： G06F13/1652
摘要： Systems and methods for arbitrating for virtual channels to prevent livelock in richly-connected multiprocessor computer system. Livelock is prevented in a multiprocessor computer system, in which each of a large plurality processing node has input links and egress links. A virtual channel is assigned to convey the communication. Communication data from the plurality of input links is buffered in cross point buffers. A subset of the cross point buffers bids for, and arbitrates, use of the same one egress link. The virtual channel of the selected communication is identified. It is determined whether any of the other communications bidding for use of the egress link are associated with the identified virtual channel and if so whether any communication has been waiting longer than the selected communication. If so, allowing that communication to use the egress link before the selected communication does.
摘要翻译： 用于虚拟通道仲裁的系统和方法，以防止富连接多处理器计算机系统中的活动锁定。 在多处理器计算机系统中防止了Livelock，其中大的多个处理节点中的每一个具有输入链路和出口链路。 分配虚拟通道来传达通信。 来自多个输入链路的通信数据被缓冲在交叉点缓冲器中。 交叉点缓冲区的一个子集为同一个出口链路的出价和仲裁使用。 识别所选通信的虚拟通道。 是否确定使用出口链路的任何其他通信招标是否与所识别的虚拟通道相关联，并且是否任何通信是否等待比选择的通信更长时间。 如果是这样，允许该通信在所选择的通信之前使用出口链路。
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7.发明申请Large scale multi-processor system with a link-level interconnect providing in-order packet delivery 审中-公开具有链路级互连的大规模多处理器系统提供按顺序分组传送公开(公告)号：US20080107116A1
公开(公告)日：2008-05-08
申请号：US11594421
申请日：2006-11-08
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L1/00 , H04L1/1806 , H04L47/34 , H04L2001/0097
摘要： A large-scale multiprocessor system with a link-level interconnect that provides in-order packet delivery. The method comprises transmitting, over a link in the defined interconnection topology, a sequence of packets in a defined order from a first node to a second node. The second node is an intermediate node in a route between the first and third node. At the first node, the transmitted packets are stored in a buffer. In response to an error in reception, the first node retrieves packets from the buffer and re-transmits them to the second node, beginning with the packet subsequent to the last packet in the sequence correctly received by the second node and continuing through the remainder of the sequence of packets.
摘要翻译： 具有链路级互连的大规模多处理器系统，其提供按顺序的分组传送。 该方法包括通过所定义的互连拓扑中的链路，以从第一节点到第二节点的定义的顺序来传输分组序列。 第二节点是第一和第三节点之间的路由中的中间节点。 在第一个节点，传输的数据包被存储在一个缓冲器中。 响应于接收中的错误，第一节点从缓冲器检索分组并将其重新发送到第二节点，从在第二节点正确接收的序列中的最后一个分组之后的分组开始，并继续通过第二节点的剩余部分 数据包的顺序。
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8.发明申请System and method for communicating on a richly connected multi-processor computer system using a pool of buffers for dynamic association with a virtual channel 失效用于在富连接的多处理器计算机系统上使用用于与虚拟通道动态关联的缓冲池的通信的系统和方法公开(公告)号：US20080107105A1
公开(公告)日：2008-05-08
申请号：US11594405
申请日：2006-11-08
IPC分类号： H04L12/56
CPC分类号： H04L49/9047 , H04L45/10 , H04L49/90
摘要： Systems and methods for communicating on a richly-connected multiprocessor computer system using a pool of buffers for dynamic association with a virtual channel. Packets are communicated in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology, in which a communication from a source processing node to a target processing node may pass through one or more intermediate nodes en route to the target processing node. A set of virtual channels is associated for each link in the interconnection topology. A first subset of buffers is dedicated for fixed correspondence to virtual channel identifiers, and a second subset of buffers is dedicated for dynamic allocation and assignment to virtual channels.
摘要翻译： 用于在富连接的多处理器计算机系统上进行通信的系统和方法，该缓冲区用于与虚拟通道动态关联。 分组在具有通过定义的互连拓扑互联的大量多个处理节点的多处理器计算机系统中通信，其中从源处理节点到目标处理节点的通信可以通过到目标处理的一个或多个中间节点 节点。 一组虚拟通道与互连拓扑中的每个链路相关联。 缓冲器的第一子集专用于对虚拟信道标识符的固定对应，并且第二子缓存器专用于动态分配和分配给虚拟信道。
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9.发明授权Computer system and method using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph 失效计算机系统和方法使用高效模块和背板平铺，通过考茨特图连接计算机节点公开(公告)号：US07660270B2
公开(公告)日：2010-02-09
申请号：US11594416
申请日：2006-11-08
IPC分类号： H04L12/28
CPC分类号： G06F15/173
摘要： Computer systems and methods using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)kn−1. The interconnections from a node x to a node y in the topology satisfy the relationship y=(−x*k−j) mod O, where 1≦j≦k, and the computing nodes are arranged onto a plurality of modules. Each module has an equal plurality of computing nodes on it. A majority of the inter-node connections are contained on the plurality of modules and a minority of the inter-node connections are inter-module connections. Inter-module connections are routed among modules in parallel on an inter-module connection plane.
摘要翻译： 使用高效模块和背板平铺的计算机系统和方法通过考茨特图连接计算机节点。 多节点计算系统包括通过具有阶数O，直径n和度k的考茨拓扑互连的大量多个计算节点。 顺序等于（k + 1）kn-1。 从拓扑中的节点x到节点y的互连满足关系y =（ - x * k-j）mod O，其中1 <= j <= k，并且计算节点被布置在多个模块上。 每个模块在其上具有相等的多个计算节点。 大多数节点间连接包含在多个模块中，并且少数节点间连接是模块间连接。 模块间连接在模块间连接平面上并行路由。
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10.发明申请Systems and methods for remote direct memory access to processor caches for RDMA reads and writes 审中-公开用于远程直接内存访问用于RDMA读取和写入的处理器高速缓存的系统和方法公开(公告)号：US20080109604A1
公开(公告)日：2008-05-08
申请号：US11594447
申请日：2006-11-08
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F12/0813 , G06F12/0879 , G06F2212/2542
摘要： The invention relates to a systems and methods for remote direct memory access to processor caches for remote direct memory access (RDMA) reads and writes. One aspect of the invention is a computer node within a multi-node computer system having a plurality of interconnected processing nodes. The computer node has least one processor associated with at least one processor cache for holding cache entries for the at least one processor. A cache interface for the remote DMA engine on the node includes logic to consult the processor cache control structure, to determine whether the processor cache has a cache entry associated with a physical address of a DMA transfer, and if so, reading from that cache entry or writing to that cache entry to service the DMA transfer.
摘要翻译： 本发明涉及用于远程直接存储器访问用于远程直接存储器访问（RDMA）读取和写入的处理器高速缓存的系统和方法。 本发明的一个方面是具有多个互连处理节点的多节点计算机系统内的计算机节点。 计算机节点具有与至少一个处理器高速缓存相关联的至少一个处理器，用于保存至少一个处理器的高速缓存条目。 用于该节点上的远程DMA引擎的高速缓存接口包括参考处理器高速缓存控制结构的逻辑，以确定处理器高速缓存是否具有与DMA传输的物理地址相关联的高速缓存条目，如果是，则从该高速缓存条目读取 或写入该缓存条目以服务于DMA传输。
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