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    Structure for connecting interconnect lines with interposed layer including metal layers and metallic compound layer
    5.
    发明授权
    Structure for connecting interconnect lines with interposed layer including metal layers and metallic compound layer 有权
    用于连接具有包括金属层和金属化合物层的插入层的互连线的结构

    公开(公告)号：US06624516B2

    公开(公告)日：2003-09-23

    申请号：US09978005

    申请日：2001-10-17

    申请人： Masahiko Fujisawa ,  Akihiko Ohsaki ,  Noboru Morimoto

    发明人： Masahiko Fujisawa ,  Akihiko Ohsaki ,  Noboru Morimoto

    IPC分类号： H01L2348

    CPC分类号： H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12). In view of this, in order to improve the adhesion especially between the second copper interconnect line (6) at the region for filling the contact hole (12) and the second conductive barrier layer (20), the metal layer (9) is provided.

    摘要翻译： 从第一铜互连线（2）和层间绝缘膜（5）的侧面观察时，依次层叠金属层（7），金属化合物层（8）和金属层（9），构成 第二导电阻挡层（20）。 作为金属层（7）和（9）的材料，可以使用原子量高于诸如钨（W）或钽（Ta）的铜的元素。 第二铜互连线（6）通过第二导电阻挡层（20）在接触孔（12）处导电地连接到第一铜互连线（2）。 由于在填充接触孔（12）的区域处，用于填充沟槽（11）的区域处的第二铜互连线（6）的体积与第二铜互连线（6）的体积的比率增加， 要集中在接触孔（12）处的拉伸应力变大。 结果，在接触孔（12）中容易产生空隙。 鉴于此，为了改善在用于填充接触孔（12）的区域和第二导电阻挡层（20）之间的第二铜互连线（6）之间的粘合性，提供了金属层（9） 。

    Method of manufacturing structure for connecting interconnect lines including metal layer with thickness larger than thickness of metallic compound layer
    6.
    发明授权
    Method of manufacturing structure for connecting interconnect lines including metal layer with thickness larger than thickness of metallic compound layer 有权
    制造包括厚度大于金属化合物层厚度的金属层的互连线的结构的制造方法

    公开(公告)号：US06780769B2

    公开(公告)日：2004-08-24

    申请号：US10464502

    申请日：2003-06-19

    申请人： Masahiko Fujisawa ,  Akihiko Ohsaki ,  Noboru Morimoto

    发明人： Masahiko Fujisawa ,  Akihiko Ohsaki ,  Noboru Morimoto

    IPC分类号： H01L2144

    CPC分类号： H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12). In view of this, in order to improve the adhesion especially between the second copper interconnect line (6) at the region for filling the contact hole (12) and the second conductive barrier layer (20), the metal layer (9) is provided.

    摘要翻译： 从第一铜互连线（2）和层间绝缘膜（5）的侧面观察时，依次层叠金属层（7），金属化合物层（8）和金属层（9），构成 第二导电阻挡层（20）。 作为金属层（7）和（9）的材料，可以使用原子量高于诸如钨（W）或钽（Ta）的铜的元素。 第二铜互连线（6）通过第二导电阻挡层（20）在接触孔（12）处导电地连接到第一铜互连线（2）。 由于在填充接触孔（12）的区域处，用于填充沟槽（11）的区域处的第二铜互连线（6）的体积与第二铜互连线（6）的体积的比率增加， 要集中在接触孔（12）处的拉伸应力变大。 结果，在接触孔（12）中容易产生空隙。 鉴于此，为了改善在用于填充接触孔（12）的区域和第二导电阻挡层（20）之间的第二铜互连线（6）之间的粘合性，提供了金属层（9） 。

    Wiring structure for an integrated circuit
    7.
    发明授权
    Wiring structure for an integrated circuit 失效
    集成电路的接线结构

    公开(公告)号：US06664641B2

    公开(公告)日：2003-12-16

    申请号：US10261653

    申请日：2002-10-02

    申请人： Akihiko Ohsaki ,  Masahiko Fujisawa ,  Noboru Morimoto

    发明人： Akihiko Ohsaki ,  Masahiko Fujisawa ,  Noboru Morimoto

    IPC分类号： H01L2710

    CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A wire width and a wiring space of each of signal wires 1 and ground/power wires 2 are determined to be a wire width W1 (the minimum wire width) and a wiring space S1, respectively. A wire width and a wiring space of the via-hole neighboring region 1a or 2a are determined to be a wire width W2 (>W1) and a wiring space S2 (

    摘要翻译： 信号线1和接地/电力线2的线宽和布线空间分别被确定为线宽W1（最小线宽）和布线空间S1。 通孔相邻区域1a或2a的线宽度和布线空间分别被确定为线宽W2（> W1）和布线空间S2（ = 0.6}。 此外，信号线1和接地/电力线2具有与宽度比（T1 / W1）等于或高于2的线材厚度T1相同的线材厚度。

    Semiconductor device, and manufacturing method thereof
    8.
    发明授权
    Semiconductor device, and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US08008730B2

    公开(公告)日：2011-08-30

    申请号：US12502008

    申请日：2009-07-13

    申请人： Shoichi Fukui ,  Noboru Morimoto ,  Yasutaka Nishioka ,  Junko Izumitani ,  Atsushi Ishii

    发明人： Shoichi Fukui ,  Noboru Morimoto ,  Yasutaka Nishioka ,  Junko Izumitani ,  Atsushi Ishii

    IPC分类号： H01L21/02

    CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.

    摘要翻译： 提供能提高半导体器件的可靠性的半导体器件的制造方法。 用于覆盖半导体衬底中形成的半导体元件的第一绝缘膜通过具有良好嵌入特性的热CVD法等形成。 通过等离子体CVD法形成第二绝缘膜以覆盖第一绝缘膜，其具有优异的耐湿性。 形成插塞以穿透第一绝缘膜和第二绝缘膜。 在第二绝缘膜上形成由具有较低介电常数的低k膜构成的第三绝缘膜。 通过镶嵌技术在第三绝缘膜中形成布线以与插头电耦合。

    Method of manufacturing contact structure
    9.
    发明授权
    Method of manufacturing contact structure 失效
    制造接触结构的方法

    公开(公告)号：US06399424B1

    公开(公告)日：2002-06-04

    申请号：US09663201

    申请日：2000-09-18

    申请人： Masazumi Matsuura ,  Kinya Goto ,  Noboru Morimoto

    发明人： Masazumi Matsuura ,  Kinya Goto ,  Noboru Morimoto

    IPC分类号： H01L2144

    CPC分类号： H01L21/76811 ,  H01L21/76801 ,  H01L21/76813 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Implemented is a method of manufacturing a contact structure having a combination of formation of a buried wiring and that of a low dielectric constant interlayer insulating film in which a connecting hole to be formed in a low dielectric constant interlayer insulating film does not turn into an abnormal shape. A fourth interlayer insulating film 11 is formed on an upper surface of a third interlayer insulating film 10. Next, patterning for a wiring trench and a connecting hole is carried out into the fourth interlayer insulating film 11 and the third interlayer insulating film 10, respectively. Then, a pattern of the connecting hole is first formed in a third low dielectric constant interlayer insulating film 9. Thereafter, a second interlayer insulating film 8 exposed in the pattern is removed and a pattern of the wiring trench is formed in the third interlayer insulating film 10. Subsequently, second and third low dielectric constant interlayer insulating films 7 and 9 are etched, and the wiring trench and the connecting hole are formed at the same time. Thus, a photoresist can be formed again without the second and third low dielectric constant interlayer insulating films 7 and 9 exposed, and an abnormal shape is generated in the connecting hole with difficulty.

    摘要翻译： 具体实施方式是制造具有掩埋布线的形成和低介电常数层间绝缘膜的组合的接触结构的方法，其中形成在低介电常数层间绝缘膜中的连接孔不会变成异常 形状。 第四层间绝缘膜11形成在第三层间绝缘膜10的上表面上。接下来，分别对第四层间绝缘膜11和第三层间绝缘膜10进行布线沟槽和连接孔的图案化 。 然后，首先在第三低介电常数层间绝缘膜9中形成连接孔的图案。然后，去除以图案露出的第二层间绝缘膜8，并且在第三层间绝缘层中形成布线沟槽的图案 随后，蚀刻第二和第三低介电常数层间绝缘膜7和9，并且同时形成布线沟槽和连接孔。 因此，可以再次形成光致抗蚀剂，而不会使第二和第三低介电常数层间绝缘膜7和9暴露，并且难以在连接孔中产生异常形状。

    Method of manufacturing semiconductor device and semiconductor device
    10.
    发明授权
    Method of manufacturing semiconductor device and semiconductor device 失效
    制造半导体器件和半导体器件的方法

    公开(公告)号：US06737319B2

    公开(公告)日：2004-05-18

    申请号：US10300579

    申请日：2002-11-21

    申请人： Noboru Morimoto ,  Masazumi Matsuura ,  Kinya Goto

    发明人： Noboru Morimoto ,  Masazumi Matsuura ,  Kinya Goto

    IPC分类号： H01L218242

    CPC分类号： H01L21/76819

    摘要： A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 &mgr;m over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, a part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG. 5 is dipped in the above-mentioned ammonia hydrogen peroxide mixture for 60 seconds to clean the surface of the interlayer dielectric film (50).

    摘要翻译： 获得制造半导体器件的方法，即使通过制造步骤的变化使FSG膜的上表面的一部分露出，也能够避免在上布线层中的布线之间的短路的产生。 在USG膜（4）在FSG膜（3）的整个表面上沉积1μm的厚度之后，USG膜（4）从上表面抛光并去除900nm的厚度， CMP方法。 此时，FSG膜（3）的上表面的一部分通过制造工序的变形而露出。 接下来，用对FSG膜（3）的蚀刻速率和对USG膜（5）的蚀刻速率基本相同的清洗液清洁层间绝缘膜（50）的表面。 这样的清洗液可以是例如NH 4 OH:H 2 O 2 :H 2 O = 1：1：20的氨过氧化氢混合物。 图1所示的结构 5浸渍在上述氨过氧化氢混合物中60秒以清洁层间电介质膜（50）的表面。