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1.发明授权Mechanism for providing over-voltage protection during power up of DC-DC converter 有权在DC-DC转换器上电期间提供过电压保护的机制公开(公告)号：US07518430B2
公开(公告)日：2009-04-14
申请号：US11091843
申请日：2005-03-28
IPC分类号： H03K17/16
CPC分类号： H02M1/36 , H02M1/32 , H02M3/156 , H02M3/1588 , Y02B70/1466
摘要： An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC-DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.
摘要翻译： 过电压保护电路防止DC-DC电源的上部开关电子装置中的短路等异常传播到下游电路。 包括耦合在上侧FET或高侧FET的输出端与下部FET的栅极之间的过电压检测电阻器的过电压保护电路可操作以感测通过上部FET的电路中的短路故障状况 初始启动系统。 响应于这种情况，下部NFET器件导通，以便将过电压状态的瞬时旁路提供给地，从而防止输出端子向下游供电电路施加过大的电压。
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2.发明授权High voltage gate driver using a low voltage multi-level current pulse translator 有权高压栅极驱动器采用低电压多电平电流脉冲转换器公开(公告)号：US07088151B1
公开(公告)日：2006-08-08
申请号：US10828610
申请日：2004-04-21
IPC分类号： H03B1/00
CPC分类号： H03K5/08 , H03K5/2472 , H03K17/6871 , H03K17/6872
摘要： A multi-level current pulse generator for driving the gates of a CMOS pair implemented using a low voltage process including a multi-level pulse translator, a current amplifier circuit, and a clamp circuit. The multi-level pulse translator generates a multi-level current pulse on at least one pulse node, each current pulse having a first large current pulse with short duration followed by at least one smaller current pulse of longer duration and operative to switch the CMOS pair with reduced average power dissipation. The current amplifier circuit amplifies the current pulses provided to the gates of the CMOS pair. The clamp circuit clamps gate voltage of the CMOS pair to prevent breakdown. In a tri-level case, a first current pulse charges and discharges gate capacitance, a second current pulse stabilizes gate voltage, and a third current pulse provides a holding current level.
摘要翻译： 一种用于驱动使用包括多电平脉冲转换器，电流放大器电路和钳位电路的低电压工艺实现的CMOS对的栅极的多电平电流脉冲发生器。 多电平脉冲转换器在至少一个脉冲节点上产生多电平电流脉冲，每个电流脉冲具有短持续时间的第一大电流脉冲，随后是至少一个较长持续时间的较小电流脉冲，并可操作以切换CMOS对 降低平均功耗。 电流放大器电路放大提供给CMOS对的栅极的电流脉冲。 钳位电路钳位CMOS对的栅极电压以防止击穿。 在三级情况下，第一电流脉冲对栅极电容进行放电，第二电流脉冲稳定栅极电压，并且第三电流脉冲提供保持电流电平。
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3.发明授权Mechanism for providing over-voltage protection during power up of DC-DC converter 有权在DC-DC转换器上电期间提供过电压保护的机制公开(公告)号：US06873191B2
公开(公告)日：2005-03-29
申请号：US10685314
申请日：2003-10-14
CPC分类号： H02M1/36 , H02M1/32 , H02M3/156 , H02M3/1588 , Y02B70/1466
摘要： An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC—DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.
摘要翻译： 过电压保护电路防止DC-DC电源的上部开关电子装置中的短路等异常传播到下游电路。 包括耦合在上侧FET或高侧FET的输出端与下部FET的栅极之间的过电压检测电阻器的过电压保护电路可操作以感测通过上部FET的电路中的短路故障状况 初始启动系统。 响应于这种情况，下部NFET器件导通，以便将过电压状态的瞬时旁路提供给地，从而防止输出端子向下游供电电路施加过大的电压。
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4.发明授权System and method of detecting phase body diode using a comparator in a synchronous rectified FET driver 有权在同步整流FET驱动器中使用比较器检测相体二极管的系统和方法公开(公告)号：US07031175B2
公开(公告)日：2006-04-18
申请号：US10797437
申请日：2004-03-10
IPC分类号： H02M7/217
CPC分类号： H02M1/088 , H02M1/38 , H02M3/1588 , H03K17/0822 , H03K17/6871 , Y02B70/1466
摘要： A body diode comparator circuit for a synchronous rectified FET driver including a sample circuit and a comparator. The FET driver has a phase node coupled between a pair of upper and lower switching FETs and is responsive to a PWM signal having first and second phases for each cycle. The sample circuit samples an initial voltage of the phase node during the first phase of the PWM signal and provides a sum voltage indicative of the initial phase voltage added to the voltage level of the phase node during the second phase of the PWM signal. The comparator compares the sum voltage with a predetermined reference voltage and provides an output indicative of an activation state of the lower FET during the second phase of the PWM signal. The FET driver turns on the upper FET when the comparator indicates that the lower FET is off.
摘要翻译： 一种用于包括采样电路和比较器的同步整流FET驱动器的体二极管比较器电路。 FET驱动器具有耦合在一对上开关FET和下开关FET之间的相位节点，并且响应于具有用于每个周期的第一和第二相的PWM信号。 采样电路在PWM信号的第一阶段期间对相位节点的初始电压进行采样，并且在PWM信号的第二阶段期间提供指示相位节点的初始相位电压的和电压。 比较器将和电压与预定参考电压进行比较，并在PWM信号的第二阶段期间提供指示下FET的激活状态的输出。 当比较器指示下部FET关闭时，FET驱动器接通上部FET。
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5.发明授权PWM-based DC-DC converter with assured dead time control exhibiting no shoot-through current and independent of type of FET used 有权基于PWM的DC-DC转换器具有确保的死区时间控制，不显示直通电流，并且与所使用的FET类型无关公开(公告)号：US06940262B2
公开(公告)日：2005-09-06
申请号：US10725764
申请日：2003-12-02
CPC分类号： H02M1/38 , H02M3/1588 , Y02B70/1466
摘要： A control circuit for a switch mode DC-DC converter contains an arrangement of monitored LGATE, UGATE and PHASE node condition threshold detectors, outputs of which are processed in accordance with a switching control operator to ensure that each of an upper FET (UFET) and a lower FET (LFET) is completely turned off before the other FET begins conduction, thereby maintaining a dead time that exhibits no shoot-through current and is independent of the type of switching FET.
摘要翻译： 用于开关模式DC-DC转换器的控制电路包含监视的LGATE，UGATE和PHASE节点状态阈值检测器的布置，其输出根据开关控制算子进行处理，以确保上FET（UFET）和 在另一个FET开始导通之前，下部FET（LFET）完全关闭，从而保持不存在直通电流的死区时间，并且不依赖于开关FET的类型。
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公开(公告)号：US5526392A
公开(公告)日：1996-06-11
申请号：US395590
申请日：1995-02-28
CPC分类号： H03K23/66
摘要： A method and circuit for selectively scaling a binary counter having N serially connected stages in which an output count from the counter is 2.sup.M times the number of clock signals that have been input to the counter. The first M stages of the counter are selectively held so that clock signals by-pass (or pass through) the first M stages without change. The M+1 stage receives each clock signal and is thereby caused to indicate that 2.sup.M clock signals have been received, when only one clock signal has, in fact, been received. The output of each stage is provided to a decoder array that provides the scaled count signal. The method and circuit find application in systems in which normal unscaled operation of the binary counter may be selectively replaced with high speed operation, such as during tests or during special operating modes. The circuit and method obviate the need for a separate high speed clock, or for adaptive circuitry in the decoder array.
摘要翻译： 一种用于选择性地缩放具有N个串行连接级的二进制计数器的方法和电路，其中来自计数器的输出计数是输入到计数器的时钟信号数目的2M倍。 选择性地保持计数器的第一M级，使得时钟信号在不改变的情况下绕过（或通过）第一M级。 实际上，当接收到一个时钟信号时，M + 1级接收每个时钟信号，从而指示已经接收到2M个时钟信号。 每个级的输出被提供给提供缩放的计数信号的解码器阵列。 该方法和电路在诸如在测试期间或在特殊操作模式期间可以用高速操作来选择性地替换二进制计数器的正常非放大操作的系统中。 该电路和方法避免了对单独的高速时钟或解码器阵列中的自适应电路的需要。
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公开(公告)号：US07023187B2
公开(公告)日：2006-04-04
申请号：US10213766
申请日：2002-08-07
IPC分类号： H02M3/158
CPC分类号： H02M3/158 , H02M1/36 , H02M3/1588 , H02M2001/007 , H02M2001/009 , Y02B70/1466 , Y10S323/901
摘要： A cascaded DC-DC converter architecture has an upstream converter stage and a downstream converter stage, which derives its input voltage from the upstream stage. Cascading the two converter stages enables functionality of control and monitoring (including soft start and overcurrent detection) circuitry of the upstream stage to be used for the downstream stage, to reduce chip area, cost, and complexity. A voltage window regulator in the downstream converter ensures that, during shutdown, its output voltage will be maintained within a prescribed window of its regulated output voltage, so that no soft start delay is needed when the second converter stage is turned back on.
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公开(公告)号：US5678030A
公开(公告)日：1997-10-14
申请号：US395863
申请日：1995-02-28
CPC分类号： G06F11/261
摘要： An emulator circuit and method of emulating operation of a computer system in which the emulator circuit may be selectively operated with memory devices that require coincident availability of data and address information during a clock cycle, and with systems that require data and address information at different times during the clock cycle. (Address information including address signals for selecting memory locations and memory control signals.) The circuit includes a data bus port for receiving data that has a transition during a clock cycle, plural address lines, each for communicating address information that has a transition during the clock cycle, an address latch control (ALC) switch with a buffer for each of the address lines, each address buffer having a latch with a first position wherein the data transition and address information transition occur at the same time during a clock cycle, and a second position wherein the address information transition leads the data transition by about one-half clock cycle, and a logical gate for receiving an ALC signal that indicates whether the first position or the second position is selected.
摘要翻译： 仿真器电路和仿真计算机系统的操作的方法，其中仿真器电路可以选择性地与在时钟周期期间需要数据和地址信息的一致可用性的存储器件以及在不同时间需要数据和地址信息的系统 在时钟周期。 （包括用于选择存储器位置和存储器控制信号的地址信号的地址信息）。该电路包括用于接收在时钟周期期间具有转换的数据的数据总线端口，多个地址线，每个地址线用于传送在 时钟周期，具有用于每个地址线的缓冲器的地址锁存控制（ALC）开关，每个地址缓冲器具有具有第一位置的锁存器，其中数据转换和地址信息转换在时钟周期期间同时发生，以及 第二位置，其中地址信息转换导致数据转换约半个时钟周期，以及逻辑门，用于接收指示是否选择了第一位置或第二位置的ALC信号。
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9.发明授权Circuit and method for synchronizing outputs of two simultaneously transmitting devices in a multiplexed communication system 失效用于在多路通信系统中同步两个同时发送设备的输出的电路和方法
公开(公告)号：US6108352A
公开(公告)日：2000-08-22
申请号：US854681
申请日：1997-05-12
IPC分类号： H04J3/06
CPC分类号： H04L12/4135 , G06F2213/0038
摘要： A circuit and method for synchronizing multiple transmitting devices in a multiplexed communication system in which transmitting nodes generate bit transitions on the multiplexed bus based on the time elapsed since the last received bit transition, and in which the synchronization is dependent only on the last received bit transition and on no other synchronization signal. The circuit and method may be used to prevent inadvertent bit transition transmission within a predetermined period of time of receipt of a bit transition.
摘要翻译： 一种用于在多路复用通信系统中同步多个发送设备的电路和方法，其中发送节点基于自上一次接收到的比特转换以来经过的时间，在复用的总线上产生位转换，并且其中同步仅依赖于最后接收的比特 转换和没有其他同步信号。 电路和方法可以用于在接收到位转换的预定时间段内防止无意的位转换传输。
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10.发明授权Multiple use timer and method for pulse width generation, echo failure detection, and receive pulse width measurement 失效多用定时器和脉冲宽度生成方法，回波故障检测和接收脉冲宽度测量
公开(公告)号：US5661736A
公开(公告)日：1997-08-26
申请号：US395591
申请日：1995-02-28
IPC分类号： G06F11/00
CPC分类号： H04L7/0008 , H04L25/4902
摘要： A method and device for timing bit transitions in a data communication system includes a multi-purpose counter/decoder responsive to transmission of bit transitions and receipt of reflections of the transmitted bit transitions to (a) indicate when the next bit transition is to be transmitted after a bit transition has been received during normal operation, (b) indicate a fault when a reflection of the transmitted bit transition is not received within a predetermined time count, and (c) determining the duration of a received bit.
摘要翻译： 用于在数据通信系统中定时位转换的方法和装置包括响应于位转换的传输和接收所发送的位转换的反射的多用途计数器/解码器，以（a）指示下一个位转换何时被发送 在正常操作期间已经接收到一个位转换之后，（b）在预定时间计数期间没有接收到发送的位转换的反射时指示故障，以及（c）确定所接收的比特的持续时间。
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